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AXI in ZYNQ

Former Member

Hi,

I am doing interface between ps to pl in ZYNQ processor. I need some clarifications on interface.
1. what is the frequency of AXI4 clock frequency.
2. for interface have 3 ways like (GPIO, ACP), I need some technical document to use the methods in vivado 2014.1.

Thanks & Regards
Ashwak ali S.

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    Hi,


        I am doing interface between PS to PL in vivado 2014.1. I need to transfer data (write and read) between PS to PL.
        hardware implementation for PS to PL:
             Blocks:
                Block RAM
                Block RAM controller
                AXI interconnect
                ZYNQ processor
    1. Implementing Block RAM for data transfer.i am using COE file in block RAM block.
    2. Block Ram controller connect Block RAM and AXI interconnect.
    3. AXI interconnect for PS to PL.

    now I want to debug(data transfer) Block RAM and Block RAM controller.
    I follow one procedure
      first use MARK DEBUG options for which one need to debug. i am using for BLOCK RAM and BLOCK RAM CONTROLLER
      run the synthesis
      create ILA file
      gemerate bit file
      export to SDK
      add signls to wave form
      run
    but the signals shows all zeros. now have any document for debug or how to debug those blocks.


    Thanks & Regads
    Ashwak ali S.
     

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  • 0

    Hi,


        I am doing interface between PS to PL in vivado 2014.1. I need to transfer data (write and read) between PS to PL.
        hardware implementation for PS to PL:
             Blocks:
                Block RAM
                Block RAM controller
                AXI interconnect
                ZYNQ processor
    1. Implementing Block RAM for data transfer.i am using COE file in block RAM block.
    2. Block Ram controller connect Block RAM and AXI interconnect.
    3. AXI interconnect for PS to PL.

    now I want to debug(data transfer) Block RAM and Block RAM controller.
    I follow one procedure
      first use MARK DEBUG options for which one need to debug. i am using for BLOCK RAM and BLOCK RAM CONTROLLER
      run the synthesis
      create ILA file
      gemerate bit file
      export to SDK
      add signls to wave form
      run
    but the signals shows all zeros. now have any document for debug or how to debug those blocks.


    Thanks & Regads
    Ashwak ali S.
     

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