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Software Application Development AXI in ZYNQ
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AXI in ZYNQ

Former Member
Former Member over 10 years ago

Hi,

I am doing interface between ps to pl in ZYNQ processor. I need some clarifications on interface.
1. what is the frequency of AXI4 clock frequency.
2. for interface have 3 ways like (GPIO, ACP), I need some technical document to use the methods in vivado 2014.1.

Thanks & Regards
Ashwak ali S.

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  • Former Member
    0 Former Member over 10 years ago

    Not sure why you would use a COE file unless it is just to initialized the BRAM contents. If you would like an example of a working design that implements an AXI Block RAM controller and a Block RAM and uses DMA to transfer data take a look at Labs 5 (to build the AXI BRAM hardware) and Lab 6 (using DMA to transfer data) of the Zynq Hardware Speedway workshop referenced above.

     

    As to why all of your signals in the Vivado Analyzer are showing zeros, are you running some program on the Zynq to exercise your BRAM hardware and provide a trigger when you are attempting the trace?

     

    You may need to spend a little time working through one of the Vivado Analyzer tutorials mentioned above or reading one of the Xilinx Users Guide listed below to be come familiar with how the debug tool works:

     

    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

     

    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug936-vivado-tutorial-programming-debugging.pdf

     

    -Gary

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  • Former Member
    0 Former Member over 10 years ago

    Not sure why you would use a COE file unless it is just to initialized the BRAM contents. If you would like an example of a working design that implements an AXI Block RAM controller and a Block RAM and uses DMA to transfer data take a look at Labs 5 (to build the AXI BRAM hardware) and Lab 6 (using DMA to transfer data) of the Zynq Hardware Speedway workshop referenced above.

     

    As to why all of your signals in the Vivado Analyzer are showing zeros, are you running some program on the Zynq to exercise your BRAM hardware and provide a trigger when you are attempting the trace?

     

    You may need to spend a little time working through one of the Vivado Analyzer tutorials mentioned above or reading one of the Xilinx Users Guide listed below to be come familiar with how the debug tool works:

     

    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

     

    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug936-vivado-tutorial-programming-debugging.pdf

     

    -Gary

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