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AXI in ZYNQ

Former Member

Hi,

I am doing interface between ps to pl in ZYNQ processor. I need some clarifications on interface.
1. what is the frequency of AXI4 clock frequency.
2. for interface have 3 ways like (GPIO, ACP), I need some technical document to use the methods in vivado 2014.1.

Thanks & Regards
Ashwak ali S.

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    Hello,

    I am new at zynq programming, I need some help.
    My Zynq design has multiple UARTs in PL which are supposed to transmit and receive 8 bit data. UART RX Custom IP blocks will transmit 8-bit data to PS, How should I set up this communication?
    Which memory should I use BRAM, DDR or registers?
    Which is the efficient way to communicate between PL and PS (in both ways) for simple byte data transfer?
    I need help in sdk programming.

    This is example Design with single UART Tx and Rx custom IP blocks.
    Inline image 1
    Such 30 UART RX and 30 UART TX are in my example as custom IPs (all in PL). PS will be processing these data frames. In first step I want to send data frames from PS side (to PL side) in sequence to each of UART TX. Data is send to next UART TX only when earlier one gives acknowledgement. After that same data frame will be transmitted from PS side to all UART TX custom IPs (PL side) in one go. So, what is to be used, as I want sequential communication for first time and then broadcast communication?
    Data will be received from outside world. While receiving from UART RX custom IP, I want to maintain some delay such that next frame will be stored till current frame is processed in PS. So, for this FIFO is good option or any better option is there, that I can give time span to data to process? I cannot use manual delay (software delay generator code) here.

    Thanks In Advance.

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  • 0

    Hello,

    I am new at zynq programming, I need some help.
    My Zynq design has multiple UARTs in PL which are supposed to transmit and receive 8 bit data. UART RX Custom IP blocks will transmit 8-bit data to PS, How should I set up this communication?
    Which memory should I use BRAM, DDR or registers?
    Which is the efficient way to communicate between PL and PS (in both ways) for simple byte data transfer?
    I need help in sdk programming.

    This is example Design with single UART Tx and Rx custom IP blocks.
    Inline image 1
    Such 30 UART RX and 30 UART TX are in my example as custom IPs (all in PL). PS will be processing these data frames. In first step I want to send data frames from PS side (to PL side) in sequence to each of UART TX. Data is send to next UART TX only when earlier one gives acknowledgement. After that same data frame will be transmitted from PS side to all UART TX custom IPs (PL side) in one go. So, what is to be used, as I want sequential communication for first time and then broadcast communication?
    Data will be received from outside world. While receiving from UART RX custom IP, I want to maintain some delay such that next frame will be stored till current frame is processed in PS. So, for this FIFO is good option or any better option is there, that I can give time span to data to process? I cannot use manual delay (software delay generator code) here.

    Thanks In Advance.

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