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Xillinux

deaxman

How do I attach anything to PS_GPIO in xillydemo?  It says multiple drivers but what if I want to write HDL code to read in a switch and set an LED?  Both are defined as PS_GPIO  (1 through 7 and 11-18 I think) but if I try to set them I get the conflict becuase they are already used in the xillybus_ins module on line 250ish.  Essentially I just want to know what to do to set a light when I flip a switch with Xillybus.  As it is I can't use any of the ports.  I have tried everything I can think of, including a seperate module that I parameterize in the bottom of xillydemo and feed in the PS_GPIOs as lines.  That approach gives no errors, but it acts as if the module isn't even there.  Thanks a ton in advance for any help!

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    Hi,

    I'll try to clarify this.

    The situation is usually that you have some signals in your Verilog / VHDL design connected to PMODs, LEDs, buttons or whatever, and they are currently connected to PS_GPIO ports.

    So what I suggest, is to expose those signals on the toplevel module (as inputs, outputs or inouts) just like any FPGA design. Then edit xillydemo.ucf, and assign those signals to the desired physical pins. Again, exactly like a regular FPGA.

    The only problem is that all PS_GPIO signals must be assigned to some physical pin on the device's grid. So the simple solution is to assign them to vacant pins. For example, the FMC connector has a lot of pins that many don't connect to anything, so the PS_GPIO signals that were evicted from their original pin assignments can get just any pin on the FMC connector. Or whatever is free.

    I hope this clarified my point somewhat.

    Regards,
       Eli

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  • 0

    Hi,

    I'll try to clarify this.

    The situation is usually that you have some signals in your Verilog / VHDL design connected to PMODs, LEDs, buttons or whatever, and they are currently connected to PS_GPIO ports.

    So what I suggest, is to expose those signals on the toplevel module (as inputs, outputs or inouts) just like any FPGA design. Then edit xillydemo.ucf, and assign those signals to the desired physical pins. Again, exactly like a regular FPGA.

    The only problem is that all PS_GPIO signals must be assigned to some physical pin on the device's grid. So the simple solution is to assign them to vacant pins. For example, the FMC connector has a lot of pins that many don't connect to anything, so the PS_GPIO signals that were evicted from their original pin assignments can get just any pin on the FMC connector. Or whatever is free.

    I hope this clarified my point somewhat.

    Regards,
       Eli

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