ZedBoard : can't use the PL under Xillinux ?

hello,

i run Xillinux on Zedboard, but i can't found any documentation to use the PL for my application

so i contact the company, which create Xillinux, check my discussion with support team of Xillinux:

------------------------------------------
hello

please can you create a forum on your website

many people, use Xillinux ( like me ), what a space to communicate and share experience and problem

second thing, i can't found, if Xillybus, make possible to run program into PL ( ZedBoard )

thank you

------------------------------------------

Hello,

A forum for Xillinux has not been set up to allow the discussions being held in zedboard.org. As for your second question, loading the PL from Xillinux is not possible as is. Even though an interface exists, it's probably very difficult to program the PL part and remain with Linux running properly.

Best regards,
Eli

----------------------------------------------------

hello

thank you for response

i didn't mean, program the PL, just how can i acces to PL ( i saw that Xillybus IP), can make this
in other mean, there is any possibility to run a program on PL, ( but the blue led is run, so PL is work )
thank you

---------------------------------------------

am waiting for your suggestion and recommendation

thank you

0 Former Member over 11 years ago

Hello,

Please refer to the documentation at Xillybus' site for more information about what solutions the company offers for communication between the PL and PS (i.e. Xillybus and Xillybus Lite):

http://xillybus.com/doc

You may also find interest in the tutorials section,

http://xillybus.com/tutorials

in particular this item (which deals with coprocessing):

http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1

Other techniques are offered by Xilinx -- but I'll leave it to others to supply you with pointers.

And please, copy-pasting emails sent in private into a public forum is a somewhat offensive act, even when their content is neutral. Unless this was the intention, I suggest refraining from that.

Regards,
Eli
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 100gma over 11 years ago in reply to Former Member

hello Eli,

thank you for your response, i come here and also i past the email chat ( without names or email address, so i respect the private condition uses, i don't think it's an " offensive act ") and others reason, is th clear what i meet as a problem so people here can understand what i want and when i until to solve it, because, i can't found a solution for my application, i tried to read all documentation, also the support team of Xillinux, they don't respond in short time, sometime, i still more than one week without response.

thank you for your recommendation, i will reback to documentation on Xillybus.

as you said that you leave some point to other support team, i post an other subject on Xilinx forum : http://forums.xilinx.com/t5/Embedded-Linux/ZedBoard-can-t-use-the-PL-under-Xillinux/td-p/457040

thank you and have a nice day
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 100gma over 11 years ago in reply to 100gma

hello,

i readed all tutorial " FPGA coprocessing: "( all part )

maybe i will found a solution to integrate this layer or driver( Xillybus IP )into my application
but i still have question about send and receive data through the FIFO of xillybus IP :( ( can i send another traitement ?

thank you
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago

Hello,

Nice to see that you've seen some progress. I suggest experimenting with Xillybus to learn it: Let your own logic interact with the FIFOs connected to the Xillybus IP core, and see what happens on the computer's side.

Regards,
Eli
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 100gma over 11 years ago

hello

i think Xillybus is the best solution for my case ( application), so i think it's possible to run a communication between PS and PL, i read all documentation ( tutorial ), now i try to found ,how can adapt the driver for my needs.

because i need to work on Xillinux as linux Os also, because i need a graphic platform to see the result of my application, i think it still 20 % to complete my project ;)

if i need some help, i will post here ( just to shared knowledgment, but if i need a specific information i will contact you by email.

have a nice day
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 9 years ago

I am working on a project on ZEDBOARD.

I was following the tutorial given on your website for : http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1.

I was able to boot up the xillinux on board and I also passed the loop back test as given in section 3.3 of this manual : http://xillybus.com/downloads/doc/xillybus_getting_started_linux.pdf.

I then modified my verilog files as per the tutrial and generated a bit file in ISE by integrating all files from HLS with the previous files. Now when I try to run the HLS demo program I am unable to get the expected output.

Even after modifying the verilog code when I try the loop back test for both 8 bit and 32 bit , I am able to successfully complete it . But when I run the HLS demo code I get the same number which I have sent in my C program and no addition or sin calculation takes place. I believe data is not being sent from PS to PL.

I would be really great full if you could please help me in this regard and suggest what are the steps I am missing in my implementation.

Thank you.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 100mihai over 8 years ago in reply to 100gma

Hi GMA,
Did you manage to program PL through Xillinux rtos ?
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 jafoste4 over 8 years ago in reply to 100mihai

Hello Mihai,
You may recieve better support asking Xillybus directly
http://xillybus.com/contact
--Josh
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel