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ZedBoard : can't use the PL under Xillinux ?

100gma

hello,

i run Xillinux on Zedboard, but i can't found any documentation to use the PL for my application

so i contact the company, which create  Xillinux, check my discussion with support team of Xillinux:

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hello

please can you create a forum on your website

many people, use Xillinux ( like me  ), what a space to communicate and share experience and problem

second thing,  i can't found, if Xillybus, make possible to run program into PL ( ZedBoard )

thank you


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Hello,

A forum for Xillinux has not been set up to allow the discussions being held in zedboard.org. As for your second question, loading the PL from Xillinux is not possible as is. Even though an interface exists, it's probably very difficult to program the PL part and remain with Linux running properly.

Best regards,
   Eli

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hello

thank you for response

i didn't mean, program the PL, just how can i acces to PL ( i saw that Xillybus IP), can make this
in other mean, there is any possibility to run a program on PL, ( but the blue led is run, so PL is work )
thank you

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am waiting for your suggestion and recommendation


thank you

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  • 0

    I am working on a project on ZEDBOARD.

    I was following the tutorial given on your website for : http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1.

    I was able to boot up the xillinux on board and I also passed the loop back test as given in section 3.3 of this manual : http://xillybus.com/downloads/doc/xillybus_getting_started_linux.pdf.

    I then modified my verilog files as per the tutrial and generated a bit file in ISE by integrating all files from HLS with the previous files. Now when I try to run the HLS demo program I am unable to get the expected output.

    Even after modifying the verilog code when I try the loop back test for both 8 bit and 32 bit , I am able to successfully complete it . But when I run the HLS demo code I get the same number which I have sent in my C program and no addition or sin calculation takes place. I believe data is not being sent from PS to PL.

    I would be really great full if you could please help me in this regard and suggest what are the steps I am missing in my implementation.

    Thank you.

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  • 0

    I am working on a project on ZEDBOARD.

    I was following the tutorial given on your website for : http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1.

    I was able to boot up the xillinux on board and I also passed the loop back test as given in section 3.3 of this manual : http://xillybus.com/downloads/doc/xillybus_getting_started_linux.pdf.

    I then modified my verilog files as per the tutrial and generated a bit file in ISE by integrating all files from HLS with the previous files. Now when I try to run the HLS demo program I am unable to get the expected output.

    Even after modifying the verilog code when I try the loop back test for both 8 bit and 32 bit , I am able to successfully complete it . But when I run the HLS demo code I get the same number which I have sent in my C program and no addition or sin calculation takes place. I believe data is not being sent from PS to PL.

    I would be really great full if you could please help me in this regard and suggest what are the steps I am missing in my implementation.

    Thank you.

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