hi i looked into lab 7 but and i created a counter ip and i use vhdl language, how i can connect my output ip counter to output my master ip in VHDL code ?? for example in below tutorial
after add component and add port map , u201Creg_data_out <= slv_reg1;u201D replace with u201Creg_data_out <= multiplier_out;" in u201Cmy_multiplier_v1_0_S00_AXI_instu201D file , i want to know what shoud change in u201Cmy_counter_v1_0_M00_AXI_VHDLu201D file after add component above 'begin' and add port map in 'user add logic' ?
hi i looked into lab 7 but and i created a counter ip and i use vhdl language, how i can connect my output ip counter to output my master ip in VHDL code ?? for example in below tutorial
after add component and add port map , u201Creg_data_out <= slv_reg1;u201D replace with u201Creg_data_out <= multiplier_out;" in u201Cmy_multiplier_v1_0_S00_AXI_instu201D file , i want to know what shoud change in u201Cmy_counter_v1_0_M00_AXI_VHDLu201D file after add component above 'begin' and add port map in 'user add logic' ?
