Zedboard printing garbage/junk over UART

Connect a scope to the serial port. Ideally one which can decode UART protocols. This will enable you to actually measure the baud rate and comprehend the data. Could be parity/baud rate/ handshake/number of data bits type issue, scoping will reveal which (if any).

MK

Perhaps the system is expecting a clock crystal source of a certain frequency and the actual crystal you are using is a different frequency, resulting in everything being "at the wrong speed".

Check that you're building things with the right target selected and clocks (source and speed) configured. Unfortunately, I have no experience with Zedboard or the latest Xilinx toolchains to give you any more guidance, but that would be what I would think of if all common baud rates are not working.

- Gough

I think what Gough Lui  mentioned could very well be the issue, because you are getting serial output, just not at the right baud rate probably. And since with the Linux image it's working fine, so it can't be a hardware issue outside of the FPGA. 

- Did you start by selecting the Zedboard as your platform when creating the vivado project? Doing like this will apply the correct board presets, including specifying correct clock frequencies

- Are you using a PS connected uart, or are you instantiating a uartlite in the FPGA fabric?

If you share your vivado block diagram, it should be a good start.

-Saad

Thanks for the response, I did select the Zedboard as the hardware platform when creating the Vivado project. And yes, I am using the PS connected to UART - the PL does not interact with the UART.

The block diagram is posted above. Here are the clock frequencies used as well:

This is the simple program running on the PS:

Ok, thanks for sharing.

Do you also have the correct UART selected in the Zynq block design and correct pins specified? Something like this:

- Saad

Yes, everything looks the same - UART 1 originally had the Pullups disabled, so I tried enabling them, and it still did not work.

Some more things to try:

1. Can you replace the print() with xil_printf() 

2. Inside Vitis SDK, under your board support package settings, can you verify that the stdin and stdout point to the correct UARTs?

Done - nothing changed.  The other things I can think of are conflicting board revisions? I have a Zedboard revision F and the board file used for the Vivado project is revision D (there is no board file for the more recent revisions). 

You can try to find the change history to see if anything related was changed. But I doubt such a major change was made between revisions. But good to rule it out anyway.

Do you have a logic analyser or oscilloscope to see what what's actually being output on the UART lines? It might help to find the root cause.

I had a quick look, and there does not seem to be any changes of relevance between revisions. Unfortunately I do not have access to any kind of analytical device at the moment. I will continue to tweak settings to see if I can get any sort of output (I just manually changed the UART baud rate to 9600 and it was still outputting junk). Thanks for all the help and the quick responses :)