This is surely a naive question. I saw how one can use a block memory generator in the block designs. It's not clear to me how one can read from or write to the block RAM using the block designs though. At least, I couldn't find any IP to accomplish this task.
Can this be done via block design? Or can it only be done via supplementary HDL code? (I lack experience when it comes to doing so via Verilog or VHDL, so I was hoping that a block design would do the trick.)
