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Block design: How to read and write to block RAM?

quadzilla

This is surely a naive question.  I saw how one can use a block memory generator in the block designs.  It's not clear to me how one can read from or write to the block RAM using the block designs though.  At least, I couldn't find any IP to accomplish this task.

Can this be done via block design?  Or can it only be done via supplementary HDL code?  (I lack experience when it comes to doing so via Verilog or VHDL, so I was hoping that a block design would do the trick.)



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  • That AXI interconnect in your diagram has to go to the Processing Subsystem (PS). Then you would use code (software) to read/write to BRAM.

    The AXI interconnect can't (I believe) be used without the PS (there are hundreds of signals between the AXI interconnect and the PS). 

  • in reply to shabaz

    I should have been more clear.  I was wondering how the FPGA fabric can write to the block RAM, after which the PS would read the contents.  (In the full diagram, the AXI interconnect is indeed connected to the PS.)

  • in reply to quadzilla

    Your block RAM should have two ports. I would point you to a blog post which shows this, but there are site issues.

    I can't see how you're aiming to use it without writing a word of HDL..

  • What's the end game here - without knowing where or what you want to write to the block ram it's not possible to answer your question.

    The kind of thing I mean is that, for example, you might have an ADC writing to the block RAM and read the data from a RAM port using the AXI controller.

    I'm working now on a system that does exactly that but it doesn't use Xilinx(AMD) FPGAs and all the FPGA stuff is done in VHDL.

    As Shabaz has said, typically you will need to use VHD or Verilog to interface the custom side of the design to the Xilinx IP stuff.

    MK

  • in reply to shabaz

    This a very standard way to use dual-port block ram. One side is wired to the processor so that it can accessed from software.  The other side is connected to some part of your fpga logic. The clocks be and the ports widths can be different. Just make one of the ports external in your IPI block diagram and you can wire that side of the memory to your HDL.

  • in reply to michaelkellett

    Sorry for the late reply.  The end game here was just a simple  preliminary test -- to have the FPGA generate data, store it in block RAM, and have the PS read this data out.  The more complicated implementation will come much later.

    Thanks for all the tips, folks.  I eventually figured out how to do this without writing any VHDL or Verilog code.  Again, because this was just a simple initial test and I was making some naive mistakes at first.

  • in reply to shabaz

    Thanks for the pointers. I did eventually manage to implement this using nothing but block designs (i.e. no HDL).  It was just a simple test though, and HDL will doubtlessly be needed after we've designed the system more thoroughly.

  • in reply to quadzilla

    If you're just writing a stream of data into the block RAM and reading it out as a stream, look into using a FIFO block.  You can write into it with a much simplified AXI Stream interface.  You won't have to worry about addresses, wrap-around, etc. 

  • in reply to padudle

    The bram port that is connected to the axi block ram controller should not have any extra pipelining enabled. For reads, he controller expects to put the address on the bram one clock cycle and get the data on the next.