Ultra96-V2 Vector Add issues

Hi guys,

I have some issues with my Ultra96-V2 board when I run and example of "vector add", the basic example that comes with Vitis.

1) I manage to compile and run the design but the performance of the kernel is very low, less than 10MOps when it is run with integer vectors. Also memory bandwidth is very low (not saturated). I tried to use higher buffers, and loop unroll with bigger factor but the performance stays very bad.

2) Also, according to the log of the compilation the kernel is synthesized for 200MHz. This should be small number, right? I noticed on the forum that there are some problem with synthesizing kernels for higher clock frequencies, but that is due to high performance of that kernel (people talked about DPU kernel). The vector-add kernel is much smaller, so I guess this is not a same issue.

3) Also, I noticed a problem in the host code when program tries to allocate buffer that is bigger than 4MB. The code exits with an allocation error.

If you have any comment on any of these issues I would really appreciate.

Thank you in advance for help.

Zoran

bhfletcher over 5 years ago

Unfortunately, I haven't done enough with Vitis to know how to help. However, this seems like a very specific Xilinx/Vitis question, so you may benefit from asking the same question over on the Xilinx forums.
https://forums.xilinx.com/

Bryan
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel
narrucmot over 5 years ago

You may want to take a look at the Vitis examples for the Ultra96-V2 board - including a pre-built example of the vector addition - posted here:
https://www.element14.com/community/community/designcenter/zedboardcommunity/ultra96?showTab=2#e14tab2
http://downloads.element14.com/downloads/zedboard/ultra96-v2/ULTRA96V2_2019_2.tar.xz?ICID=ultra96v2-datasheet-widget

http://downloads.element14.com/downloads/zedboard/ultra96-v2/u92v2vadd_2019_2.tar.xz?ICID=ultra96v2-datasheet-widget

--Tom
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel
zorjak over 5 years ago in reply to narrucmot

Thanks for your posts guys,

I took the files from avent HDL and petalinux git repositories and I have built petalinux image with the latest commit.
I can confirm that with these latest repo changes, the issue with max array size of 4MB has been solved. Now I can allocate arrays with much higher sizes. I don't know what exactly solved the issue but it does not exist anymore.

If I add ```--kernel_frequency 500``` in the settings of v++ kernel compiles with higher frequency (it achieves more than 650MHz). I am new with Xilinx tools but it seems that for embedded systems when you use HLS with Vitis you have to add kernel frequency as a flag in compiler. I tough that compiler by default tries to achieve max frequency but it seems that it just tries to satisfies the default (which is 150MHz for ultra96-v2).

I noticed some other warnings that I will try to solve and I will test the performance again. I will write here if I have success.

Tom, thanks again for the links. I will check. It seems very useful.

Best regards,
Zoran
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel
zorjak over 5 years ago in reply to narrucmot

Hi Tom,

One question.
Did you test pefromance of the vector add example that you sent me? Is it possible to do that? I am interested how many MOPs are executed and what is effective memory bandwidth.

I wrote a simple host code (based on the vitis vector example) and I used binary that you sent me.
I added a simple host profiling code and I got very small numbers (6MOPs and around 75MBps memory bandwidth). Is it possible that you somehow test the pefromance of the vector add that you provided and to make some comment on that?

Thank you very much in advance,
Zoran
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel