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Problem about access the output signal of vivado blocks

pmuproject

Hello there,

I'm current building a clock source in vivado by using the clk_wiz module. The output clock is the clk_out1 pin on the clk_wiz module. When I finish the design of vivado and export it to SDK I found that there is nothing can be used related to the clk_out1 pin. Just woundering how can I access to the clk_wiz and output the clk_out1 signal to a gpio pin in SDK?

Regards,

Han

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  • 0 in reply to jafoste4

    Hello Josh,

    Thanks for your reply. I can access my PL GPIO now. But the problem still here. Could you plz help me to check my work procedure?

    First I creat the bd and put zynq Ultrascale+ IP and clk_wiz IP and makes external for the clk_wiz output pin which is named clk_wiz_out. Then I go to synthesis and fix the clk_wiz_out to package pin D7 which is my HD_GPIO_0. Then the bitstream is generated and exported hardware. Then launch SDK. In SDK first I created the board support package. Then I tried to created both FSBL project and hello world project and programm FPGA and run the codes.  But I still get nothing of my GPIO pin. Did I missed anything? Is there any solution to fix this problem? Thanks!

    Regards,

    Han

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