Problem about access the output signal of vivado blocks

Hello there,

I'm current building a clock source in vivado by using the clk_wiz module. The output clock is the clk_out1 pin on the clk_wiz module. When I finish the design of vivado and export it to SDK I found that there is nothing can be used related to the clk_out1 pin. Just woundering how can I access to the clk_wiz and output the clk_out1 signal to a gpio pin in SDK?

Regards,

Han

0 jafoste4 over 7 years ago

hello Han,
Did you make your signal external and write constraints to output the signal to a specific GPIO pin?
-Josh
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0 pmuproject over 7 years ago in reply to jafoste4

Hi Josh,
Yes I made a external of the output clock from clk_wiz but I didn't write constraints for it in my .xdc file. I wrote all the gpio pins with the correspoding information from Ultra96 Schematic. Do I need to connect the output signal to the GPIO Pin directly such as :
set_property PACKAGE_PIN D10 [get_ports { clk_out1_1 }];
or set_property MIO36_PS_GPIO1_0 [get_ports {clk_out1_1 }];
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0 jafoste4 over 7 years ago

Hello pmuproject,
Yes you will need to route the signal directly to the GPIO similarly to how you are showing above. Unfortunatly you will only be able to access PL GPIO, so do not use the MIO36 constraint you wrote above.
-Josh
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0 pmuproject over 7 years ago in reply to jafoste4

Hi Josh,
Thanks for your reply. In my understanding the HD and HP banks of gpio pins are PL GPIO, am I right? I just write the constraint as below:
set_property PACKAGE_PIN D7 [get_ports {clk_out1_1 }]; # "D7.HD_GPIO_0"
And I exported it to SDK and tried to output the clk_out1_1 signal on pin 3 which is the pin HD_GPIO0. First I tried use a Hello World code and it didn't work. Then I tried to set the direction of HD_GPIO0 to see the results. But the problem is I don't know the base address of HD_GPIO0 and the ID defined in xparameter.h. How can I output it to the HD_GPIO0 pin? Thanks for your help!
Regards,
Han
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0 jafoste4 over 7 years ago

Hello Han,
Please reference this http://blog.dev-flow.com/en/9-controlling-the-pl-from-the-ps-on-zynq-7000/
-Josh
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0 pmuproject over 7 years ago in reply to jafoste4

Hello Josh,
Thanks for your reply. I can access my PL GPIO now. But the problem still here. Could you plz help me to check my work procedure?
First I creat the bd and put zynq Ultrascale+ IP and clk_wiz IP and makes external for the clk_wiz output pin which is named clk_wiz_out. Then I go to synthesis and fix the clk_wiz_out to package pin D7 which is my HD_GPIO_0. Then the bitstream is generated and exported hardware. Then launch SDK. In SDK first I created the board support package. Then I tried to created both FSBL project and hello world project and programm FPGA and run the codes. But I still get nothing of my GPIO pin. Did I missed anything? Is there any solution to fix this problem? Thanks!
Regards,
Han
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