xilinx-ultra96-prod-dpu1.4-desktop-buster-2019-05-31.img.zip
Prebuilt image for Ultra96 not working with Ultra96 V2
The only difference between V1 and V2 is DDR Timing?
Is there an unofficial image for V2?
Regards,
xilinx-ultra96-prod-dpu1.4-desktop-buster-2019-05-31.img.zip
Prebuilt image for Ultra96 not working with Ultra96 V2
The only difference between V1 and V2 is DDR Timing?
Is there an unofficial image for V2?
Regards,
Hi,
I can confirm we got this working on the Ultra96-V2. However we cannot release this unoffical image at this time.
-Josh
Dear Josh,
Is there any progress in DPU project?
Regards, Eugene.
Yes, Josh,
I would like to know when this project will be released as well.
Thank You
Tom
Hi Tom,
We have uncovered a hardware issue with the Ultra96-V2 board that appears to affect designs like this one that use most of the PL and are computationally intensive. We are debugging this issue now and plan to have it addressed, and this design released, by the end of October. Stay tuned for further updates...
Cheers,
Tom
Tom,
Thank you very much for the reply. I don't envy you your debug task.
I already spent $$ on the ultra96v2, as it is my want to be on the most current hardware. However, perhaps I did not do such a smart thing because, as I am finding out, lots of projects "out there" for the ultra96 are not forward compatible with the v2. At this point, rather than suffer the slings and arrows of the new hardware, would you recommend purchasing the V1 instead?
Cheers,
Tom
The DPU will work on Ultra96-V2 with datecode earlier than August 2019 at a maximum rate of 195 MHz. This was due to a programmable current threshold setting in our power circuitry that was too pessimistic and not because of a real hardware limitation. For reference, the Ultra96-V1 operates at 255 MHz.
We are working with Xilinx now. By modifying the current threshold and adding an improved heatsink solution, we've been able to run faster than 255 MHz. We are testing now for stability as we don't want users to get frustrated. We are working on a procedure so existing users can update their programmable power supplies. We are also working to get the new heatsink in stock. I expect this will take us ~2 months to get all the details worked out.
We do not want engineers to have a poor experience with lack of performance on the earlier Ultra96-V2 due to the frequency limitation. Again, the limitation is NOT because of the ZU+ fabric or the DPU design. If you are satisfied to work at <195 MHz, then message me. I will see if Xilinx will release a preliminary version on a user-by-user basis.
Bryan
Bryan,
Thank you for the update. Evidently, you and your team are putting a lot of work into this.
At this stage in my development process, I am content to work at rates less than 195 MHz. I purchased my Ultra96-V2 about a month ago, early September, so it is probable that it was manufactured prior to August 2019. However, even under a magnifying glass, I could not see a stamped date code, on either side of the board. So, it is somewhat of a guess.
Please ask Xilinx to release a "preliminary version" (and I am assuming of the DPU) . I was considering purchasing the ZCU104 from Xilinx but I seriously wanted to used something in a smaller footprint to begin with and, I did not want to consider the V2 a $300 loss while spending the nearly $1K for the 104.
Thank You
Tom
Hi Bryan,
I am satisfied to work at <195 MHz. Could you give me a preliminary version about DPU.
My email is shixiaoke1836@dingtalk.com.
Thanks.
Shi
prornetheus wrote:
xilinx-ultra96-prod-dpu1.4-desktop-buster-2019-05-31.img.zip
Prebuilt image for Ultra96 not working with Ultra96 V2
The only difference between V1 and V2 is DDR Timing?
Is there an unofficial image for V2?
Regards,
Why would you expect an image built for certain hardware to work on a changed hardware platform? It makes no sense when you understand the same hold for PC's. An AMD system drive would not work in an Intel built system...
Introducing Ultra96-V2 <---- List of the many changes
The mention of AVNET's V2 indicates that DDR's suppliers have changed.
and if the problem is simply DDR Timing, Changing timing parameter solves it.
Do not be rude.