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PL-PS configuration in Ultra96 v2

bengugu

Hello,

 

With ultra96-v1 I can establish PS-PL axi interconnection and transfer processed data from PL to PS DDR, but no luck with Ultra96-V2.

 

I have changed the PS DDR configuration according to

LPDDR4 Memory differences between Ultra96-V1 and Ultra96-V2

And I also tried to lower the clock frequency for the data transmission but nothing helped.

Can I have some hint for solving this problem?

Is there anything else has to be changed for V2 from V1?

 

Thanks

  • 0

    After making the memory changes, did you first perform a basic memory test to make sure everything was working?

     

    There are no other changes at the FSBL level than the memory controller parameters between V1 and V2. The only other major change is the Wi-Fi Radio Linux drivers, so I don't think that is the issue here.

     

    Bryan

  • 0 in reply to bhfletcher

    Hi Byran,

     

    I have been stucked for this issue for quite long...

    And finally i get some progress but still havent solved this problem.

     

    As it is mentioned before I want to establish PS-PL axi interconnection and transfer processed data from PL to PS DDR.

    The DDR address i shared for the PL side from 0x30000000 to 0x80000000.

     

    The situation is here:

    1. I created the BOOT.BIN and image.ub using the provide ultra96 v2 bsp and my design *.hdf.

    2. Boot the board using SD card.

    3. Run the *.elf

    This didn't work and it can be checked in my elf that the DDR didnt response to anything.

     

    Then I tried to debug and used the vivado hardware manager to directly program the device using the bitstream file.

    And suprisingly everything is ok!

    I checked the signals in the waveform moniter and everything seems to be fine, which proves that the design should be ok.

     

    As a beginner of the zynqmp design, i dont know what is the difference here which caused the different result.

    Is there anything wrong during the petalinux build or something missing in the device tree/fsbl?

     

    Regards,

    Gu

  • 0 in reply to bhfletcher

    Hi

     

    Since I can make every works ok by using vivado hardware manager to directly program the device using the bitstream file.

    I tried another way to prove my thought.

    I enabled the fpga manager in the petalinux-config and create the BOOT.BIN without bitstream inside it.

    After the board is booted, i used the fpga-manager in the linux OS and program the device with the *.bit.bin file I put in the SD card, which is generated by the bootgen command in the petalinux.

    And as it is expected everything works ok.

     

    So, I think maybe there is something need to be modified for the fsbl.elf before the petalinux-build.

    The last thing left for what I can try is to create the fsbl.elf in the vivado SDK and overwrite it in the petalinux-build images/linux then do the package thing to create BOOT.BIN.

     

    Do you have any other advices?

    Gu

  • 0 in reply to bengugu

    Hi there,

     

    Have you gone through any of the training courses that we created?  There are some details around creating a boot.bin, however for the most part the tool takes care of everything for you.  To me, it sounds like you are swapping the order of the pieces in the boot.bin, or possibly not actually loading them by hand.

     

    To explain why, if you just create your Vivado design, then export to SDK directly from the Vivado tool, everything will be setup for you in SDK without the need to do anything.

     

    --Dan

  • 0 in reply to drozwood90

    Hi Dan

     

    Thank you for the reply.

    The thing is that I want to use petalinux OS in my design so i am now creating the BOOT.bin and image.ub with the petalinux 2018.3 tool.

    After creating the project with Ultra96 v2 bsp, i replaced the hdf with my own design and i followed the manual of UG1144 to create boot files.

    Am I am aware of that almost everything can be handled by the petalinux tool.

     

    I think the order in boot.bin is a good point to check. Can you tell me how to check or configure it in petalinux tool?

     

    Regards,

    Gu

  • 0 in reply to bengugu

    Hi Gu,

     

    Can you share with me the steps you went through - the commands you ran - to import your new custom hw platform into the PetaLinux project?  Was the bitstream included in the imported HDF?  It may not have been as the bitstream is not included in the HDF by default.

     

    --Tom

  • 0 in reply to narrucmot

    Hi Tom,

     

    The bitstream should have been included in the HDF because after i boot the board with the BOOT.BIN I created, i can see the blue led which means the board is programmed.

     

    After I created a new template with the provided bsp.

    The command I went through:

    1. petalinux-config --get-hw-description=../ULTRA96_V2.sdk

    => the customized hdf file is included in ULTRA96_V2.sdk, i didnt change any configuration and just go next step

    2. petalinux-build

    3. petalinux-package --boot --force --fsbl images/linux/zynqmp_fsbl.elf --fpga images/linux/system.bit --u-boot

    4. copy the BOOT.BIN and image.ub to the SD card

     

    And as i have mentioned this is not working, i have to reprogram the fpga with the bitstream file to make my application work.

    I wonder is there something i have to modificate before i do the petalinux-build

     

    Regards,

    Gu

  • 0 in reply to narrucmot

    Hi Tom,

     

    As Daniel mentioned the problem maybe caused by the inappropriate order of the pieces in the boot.bin,

    can you how to check or configure it in petalinux?

    Currently I am using the default configuration of the bsp.