PL-PS configuration in Ultra96 v2

Question

Hello,

With ultra96-v1 I can establish PS-PL axi interconnection and transfer processed data from PL to PS DDR, but no luck with Ultra96-V2.

I have changed the PS DDR configuration according to

LPDDR4 Memory differences between Ultra96-V1 and Ultra96-V2

And I also tried to lower the clock frequency for the data transmission but nothing helped.

Can I have some hint for solving this problem?

Is there anything else has to be changed for V2 from V1?

Thanks

bengugu · Answer

Hi Byran,

I have been stucked for this issue for quite long...

And finally i get some progress but still havent solved this problem.

As it is mentioned before I want to establish PS-PL axi interconnection and transfer processed data from PL to PS DDR.

The DDR address i shared for the PL side from 0x30000000 to 0x80000000.

The situation is here:

1. I created the BOOT.BIN and image.ub using the provide ultra96 v2 bsp and my design *.hdf.

2. Boot the board using SD card.

3. Run the *.elf

This didn't work and it can be checked in my elf that the DDR didnt response to anything.

Then I tried to debug and used the vivado hardware manager to directly program the device using the bitstream file.

And suprisingly everything is ok!

I checked the signals in the waveform moniter and everything seems to be fine, which proves that the design should be ok.

As a beginner of the zynqmp design, i dont know what is the difference here which caused the different result.

Is there anything wrong during the petalinux build or something missing in the device tree/fsbl?

Regards,

Gu

bengugu · Answer

Hi Since I can make every works ok by using vivado hardware manager to directly program the device using the bitstream file. I tried another way to prove my thought. I enabled the fpga manager in the petalinux-config and create the BOOT.BIN without bitstream inside it. After the board is booted, i used the fpga-manager in the linux OS and program the device with the *.bit.bin file I put in the SD card, which is generated by the bootgen command in the petalinux. And as it is expected everything works ok. So, I think maybe there is something need to be modified for the fsbl.elf before the petalinux-build. The last thing left for what I can try is to create the fsbl.elf in the vivado SDK and overwrite it in the petalinux-build images/linux then do the package thing to create BOOT.BIN. Do you have any other advices? Gu