Is C based Vivado high level synthesis a viable option to develop complex PL systems on Zynq? Does it have many limitations versus VHDL or Verilog?
Is C based Vivado high level synthesis a viable option to develop complex PL systems on Zynq? Does it have many limitations versus VHDL or Verilog?
This is really weird Tom, some one is impersonating you and asking questions in your name but they seem to be hiding it from you 
I have some suggestions:
1) get a friend to post the FAQs for you and then you can "answer" them
2) pay someone to ask the FAQs for you
3) Ask the questions and see if anyone can answer them for you.
4) Be all up front about it and post "Toms favorite FAQs"
5) Maybe be a bit less Xilinx in the answers.
So instead of
narrucmot wrote:
Yes! C based HLS is a great methodology for creating custom IP like accelerators to run in the ZU+ PL. Xilinx UG1399 and UG1393 will be a good place to start.
How about:
"It's really difficult to to develop complex PL systems in VHDL or Verilog. Xilinx's HLS is loosely based on C and has a go at making it more like conventional programming but that still doesn't make it easy. HLS can be useful but has the downside of being a Xilinx proprietary tool and non portable. You need to look carefully at the fit between the problem, the tool and your own skillset to choose. "
MK
