Vitis vadd example hardware emulation on u96v2_sbc_dualcam exiting with error

Hi,

I successfully built the u96v2_sbc_dualcam design according to

https://www.hackster.io/AlbertaBeef/stereo-face-detection-with-the-dual-camera-mezzanine-8c7baf#toc-appendix-1---rebuilding-the-design-6.

Now I want to add my own accelerator instead of the xilinx dpu. For that, I follwed the vadd tutorial

https://github.com/Xilinx/Vitis-Tutorials/tree/2021.2/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow, but unfortunately, the building process exits with an error:

link steps log:

ERROR: [XSIM 43-3409] Failed to compile generated C file ../../../../prj.ip_user_files/bd/u96v2_sbc_dualcam/ip/u96v2_sbc_dualcam_v_proc_ss_scaler_0_0/bd_0/sim/bd_11ff_sci.cxx.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...

vivado.log:

ERROR: caught error: xsc -c --gcc_compile_options -DBOOST_SYSTEM_NO_DEPRECATED --gcc_compile_options -I../../../../prj.ip_user_files/bd/u96v2_sbc_dualcam/ip/u96v2_sbc_dualcam_v_proc_ss_scaler_0_0/bd_0/sim -I/tools/Xilinx/Vivado/2021.1/tps/boost_1_72_0 -work xil_defaultlib -f u96v2_sbc_dualcam_wrapper_xsc.prj
ERROR: [XSIM 43-3409] Failed to compile generated C file ../../../../prj.ip_user_files/bd/u96v2_sbc_dualcam/ip/u96v2_sbc_dualcam_v_proc_ss_scaler_0_0/bd_0/sim/bd_11ff_sci.cxx.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...

How to fix that? Thank you!

Cheers,

Betty

0 bettyET over 3 years ago

Is there anyone who can help?
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0 albertabeef over 3 years ago

Betty,
First, are you using different versions ?
The vitis platform you are refering to was created with 2021.1, but the vadd example you are refering to was created with 2021.2.
There is no support for mixing versions, as this is known to have unexpected issues.

There is a new version of the dual camera design for 2021.2 : https://avnet.me/vitis-ai-2.0-dualcam

Regards,
Mario.
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0 bettyET over 3 years ago in reply to albertabeef

Hi Mario,

thanks for your reply.

No, actually I built the vadd kernel with 2021.1, too. Anyways, its exactly the same rtl sources for 2021.1 and 2021.2.

Everything works when building for the hardware, but not for hardware emulation.

Cheers,

Betty
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0 bettyET over 3 years ago in reply to albertabeef

Hi Mario,

the problem seems to be missing include paths when executing /Emulation-HW/binary_container_1.build/link/vivado/vpl/prj/prj.sim/sim_1/behav_waveform/xsim/compile.sh:

In file included from ../../../../prj.ip_user_files/bd/u96v2_sbc_dualcam/ip/u96v2_sbc_dualcam_v_proc_ss_scaler_0_0/bd_0/sim/bd_11ff_sci.cxx:2:0:
../../../../prj.ip_user_files/bd/u96v2_sbc_dualcam/ip/u96v2_sbc_dualcam_v_proc_ss_scaler_0_0/bd_0/sim/bd_11ff_sci.h:5:18: fatal error: xtlm.h: No such file or directory
#include "xtlm.h"

So I found out that when adding "/tools/Xilinx/Vivado/2021.1/data/xsim/ip/common_cpp_v1_0/include" and "/tools/Xilinx/Vivado/2021.1/data/xsim/ip/xtlm/include" to the include paths I can rerun compile.sh without error. However, compile.sh is a generated file... Do you know where I can add the missing include paths into the vitis flow?

Thank you

Betty
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