Can I use MIO pins to route PL external ports? (without involving the PS)

I would like to know if I can use MIO pins to route PL external ports? (without involving the PS). Also if possible I would like to know if anyone could send me an example.

The reason of asking this is because there 14 MIO pins on the ultra96 Mezzanine ports, I will like to use them from the PL using the MPSoCa as a normal FPGA

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flyingbean over 2 years ago +3

It is an interested question. MIO pins are hardened IOs for the ASIC cores on PS side. Please read Xilinx document: UG1085 Table 28-1. It is similar as using the multiplex IOs on a processor or micro-controller…
shabaz over 2 years ago in reply to lord_rafa +3

It's all explained here: https://www.xilinx.com/video/soc/mio-emio-configuration-zynq-7000.html As you can see, the MIO pins are permanently allocated to the PS. It's in the first slide there. So, obviously…

Jan Cumps over 2 years ago

Is your goal to have 14 additional package balls available to the PL?
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lord_rafa over 2 years ago in reply to Jan Cumps

Yup, at the end that would be the goal, also I am exploring till with extension the MpSoC is required. I presume that acceding those pins directly would be faster that copying info in memory by software.

I also posted a similar question but since they affect to different parts, I would like to keep this two separated
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flyingbean over 2 years ago

It is an interested question. MIO pins are hardened IOs for the ASIC cores on PS side. Please read Xilinx document: UG1085 Table 28-1. It is similar as using the multiplex IOs on a processor or micro-controller. If you digging deeper on Xilinx document regarding the hardware design for Zynq UltraScale+ technology, there are a lot of level-shifters between PS and PL side. So you basically cannot use MIOs for PL logic design directly. However, you might be able to build a subsystem and include PS for data transferred from PL to PS, then to MIOs or vice versa , which apparently were not you wanted.
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lord_rafa over 2 years ago in reply to flyingbean

Thanks for your answer. So If I understood correctly if I want to use MIOx from the PL, I would need to set the PS to route GPIO to MIOx and then use AXI to connect the PL logic to the GPIO memory, is this right? is there any other mechanism a part from GPIOMEM-AXI-PL?
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shabaz over 2 years ago in reply to lord_rafa

It's all explained here: https://www.xilinx.com/video/soc/mio-emio-configuration-zynq-7000.html

As you can see, the MIO pins are permanently allocated to the PS. It's in the first slide there. So, obviously, if you wish to make use of those pins, then you have to make use of the processor.
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lord_rafa over 2 years ago in reply to shabaz

Thank you flyingbean and shabaz this solves pretty much my about this topic. I would like to have a better understanding about AXI and how the PS-PL can communicate to each other but that is for another topic.
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