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Ultrazed Hardware Design Use the SDI and HDMI/DisplayPort ports
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  • sdi
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Related

Use the SDI and HDMI/DisplayPort ports

francaprgonz
francaprgonz over 4 years ago

Hello. I'm new with Ultrazed -EV. Im trying to modify the VCU Example Design (2018.3) as starting point. My main idea is to inyect a signal in the HDMI/Display port and send it directly to SDI output. Someone have experience using both ports ? Do you have some example to start with this ?


So the main idea:
Input : HDMI or DisplayPort ( My real input is a DVI)
Output: SDI  (3G HD-SDI)

Best.


FC

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  • drozwood90
    drozwood90 over 4 years ago +1 suggested
    HI there, While I can't support you very much as this is not released, I would suggest you take a look at the VCU design that we already ported for 2020.2 tools: https://github.com/Avnet/petalinux/blob…
  • drozwood90
    drozwood90 over 4 years ago in reply to francaprgonz +1 suggested
    Hi there, You can take that clock and pipe it back out with appropriate divisors. Although, personally, if the GTH is running (use something like IBERT), then it is connected. --Dan
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  • drozwood90
    0 drozwood90 over 4 years ago

    HI there,

     

    While I can't support you very much as this is not released, I would suggest you take a look at the VCU design that we already ported for 2020.2 tools:

    https://github.com/Avnet/petalinux/blob/2020.2/scripts/make_uz7ev_evcc_hdmi_v.sh

     

    Pull our repositories down and checkout the 2020.2 branches, then run that script.  That will get you a design.  I am not complete with the documentation on this, but after booting, if you press SW1 the HDMI output should turn BLUE @ 4KUHD output.  From there, you can run the various scripts that are included in the root home and test this out.

     

    That's probably the fastest way to get you to the point of messing around.

     

    --Dan

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  • francaprgonz
    0 francaprgonz over 4 years ago in reply to drozwood90

    Hi Daniel, I saw the project and i see that just "HDMI_RX_CLK_P_IN " (PIN "set_property PACKAGE_PIN B10") is going inside the FPGA. They dont need both ? (differential pins).
    Im having issues related with this but in my proyect. This  "HDMI_RX_CLK_P_IN " clock should be 148.5MHz ? because in my case i need that CLK for SDI.

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  • drozwood90
    0 drozwood90 over 4 years ago in reply to francaprgonz

    HI there,

     

    Inside the FPGA, you do not need both.  Sorry for how I am going to word this, but you only really need both if you need both.  You want both for SI, but using clock capable pins you get a slew of features that you can take advantage of.

    I am not 100% certain, but it sounds reasonable to me that you would want that to be the SDI clock.

     

    --Dan

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  • francaprgonz
    0 francaprgonz over 4 years ago in reply to drozwood90

    How can i check if im geting the clk signal inside the FPGA ? If i try to connect in ILA (IBUF_OUT), it say that i can connect just in GTH pins, so i dont know how validate it.

     

    set_property IOSTANDARD LVDS [get_ports {CLK_IN_D_0_clk_p}]

    set_property PACKAGE_PIN D10 [get_ports {CLK_IN_D_0_clk_p}]

     

    image

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  • drozwood90
    0 drozwood90 over 4 years ago in reply to francaprgonz

    Hi there,

     

    You can take that clock and pipe it back out with appropriate divisors.

    Although, personally, if the GTH is running (use something like IBERT), then it is connected.

     

    --Dan

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  • drozwood90
    0 drozwood90 over 4 years ago in reply to francaprgonz

    Hi there,

     

    You can take that clock and pipe it back out with appropriate divisors.

    Although, personally, if the GTH is running (use something like IBERT), then it is connected.

     

    --Dan

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  • francaprgonz
    0 francaprgonz over 4 years ago in reply to drozwood90

    Hi Daniel,
    Thank you for answer me. I'm continue having problems with the clock. Do you know someone that work with the SDI part of the ultrazed ? I'm struck like 2 weeks with the same problem.
    Best.
    FC




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