Hi everyone,
I recently recreated the Analog Devices reference design for the HDMI-Transmitter in a PlanAhead project and it currently works with a pixel clock of 148.5MHz (1080p) with my own code I've written in the SDK.
But yesterday I saw that the synthesis tools complain about a timing constraint that wasn't met during synthesis. It's clk_fpga_1 which is, like in the sample project project, set to 200MHz. It's the main clock for the VDMA-AXI-Interconnect and the VDMA core itself. The tools state, that the maximum frequency for this signal is at 100.01MHz. Why does my design even work?
So, I changed the clock in the XPS to 100MHz, just to see what happens. As it turns out, the tools still complain that the timing is not met at 200MHz. Why? I just set it to 100MHz. Even if I remove all intermediate files, a synthesis run creates, from the project, I get the same message. Funnily enough, the design still works.
If I grep for the constraints, I find that the file 'simple_linux.srcs/sources_1/edk/system/implementation/processing_system7_0_wrapper/processing_system7_0_wrapper.ucf' in the project contains the correct timing constraint, but the generated UCF-Files in the design ('simple_linux.runs/impl_1_2/system_stub.ucf' for example) then contain the wrong 200MHz constraint.
Is this a bug in the tools?
