element14 Community
Search
Register
Log In
Site
Search
Log In
Register
Community Hub
Community Hub
What's New on element14
Feedback and Support
Benefits of Membership
Personal Blogs
Members Area
Achievement Levels
Learn
Learn
Ask an Expert
eBooks
element14 presents
Learning Center
Tech Spotlight
STEM Academy
Webinars, Training and Events
Learning Groups
Technologies
Technologies
3D Printing
FPGA
Industrial Automation
Internet of Things
Power & Energy
Sensors
Technology Groups
Challenges & Projects
Challenges & Projects
Design Challenges
element14 presents Projects
Project14
Arduino Projects
Raspberry Pi Projects
Project Groups
Products
Products
Arduino
Avnet Boards Community
Dev Tools
Manufacturers
Multicomp Pro
Product Groups
Raspberry Pi
RoadTests & Reviews
Store
Store
Visit Your Store
Choose another store...
Europe
Austria
(German)
Belgium
(Dutch, French)
Bulgaria
(Bulgarian)
Czech Republic
(Czech)
Denmark
(Danish)
Estonia
(Estonian)
Finland
(Finnish)
France
(French)
Germany
(German)
Hungary
(Hungarian)
Ireland
Israel
Italy
(Italian)
Latvia
(Latvian)
Lithuania
(Lithuanian)
Netherlands
(Dutch)
Norway
(Norwegian)
Poland
(Polish)
Portugal
(Portuguese)
Romania
(Romanian)
Russia
(Russian)
Slovakia
(Slovak)
Slovenia
(Slovenian)
Spain
(Spanish)
Sweden
(Swedish)
Switzerland
(German, French)
Turkey
(Turkish)
United Kingdom
Asia Pacific
Australia
China
Hong Kong
India
Korea
(Korean)
Malaysia
New Zealand
Philippines
Singapore
Taiwan
Thailand
(Thai)
Americas
Brazil
(Portuguese)
Canada
Mexico
(Spanish)
United States
Can't find the country/region you're looking for? Visit our
export site
or find a
local distributor
.
Translate
Profile
Settings
Products
Dev Tools
Avnet Boards Community
Avnet Boards Forums
More
Cancel
Avnet Boards Forums
Using Xilinx Tools Forum
Forum
Documents
Members
Mentions
Sub-Groups
Tags
More
Cancel
New
Avnet Boards Forums requires membership for participation - click to join
Threads
462 Discussions
Frequently Asked
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings
Answered
over 2 years ago
Petalinux 2021.2 and TFTP server address
Not Answered
over 3 years ago
Ultra 96 Xilinx ZYNQ UltraSCALE Software and Installation Support
Not Answered
over 3 years ago
How to program Axi SPI using Arty7 - 35T
Not Answered
over 2 years ago
Does changing RX lane rate between 300 and 600 Mbps change RX CSI-2 MIPI D-PHY IP topology (HDL code of soft IP)? Good Day Dear , In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which...
Not Answered
over 2 years ago
Using Xilinx Tools Forum
By title
By last reply date
By thread date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions and discussions
Unanswered questions and discussions
Answered questions and discussions
Questions with suggested answers
Questions and discussions with no replies
Not Answered
ZCU111 No TCP Connection
0
249
views
0
replies
Started
over 1 year ago
by
XXXLIMYOONA
Not Answered
Microzed7010 rev H board files
0
522
views
2
replies
Latest
over 1 year ago
by
RAJAT99
Not Answered
ADC to DMA to DAC
0
426
views
0
replies
Started
over 1 year ago
by
RAJAT99
Not Answered
Xilinx Article "PS IIC and AXI IIC debug techniques" from this link https://support.xilinx.com/s/article/1135303?language=en_US
0
329
views
0
replies
Started
over 1 year ago
by
RAJAT99
Not Answered
Ultrazed-EG IOCC stopped at u-boot
0
447
views
1
reply
Latest
over 2 years ago
by
100yogesh
Not Answered
Cannot get symbol location information. No object location info found in DWARF data
0
707
views
0
replies
Started
over 2 years ago
by
RAJAT99
Answered
Zedboard rev B Board files
0
1044
views
4
replies
Latest
over 2 years ago
by
RAJAT99
Not Answered
Tutorial 09 PL I2C PMOD from this link.
0
447
views
0
replies
Started
over 2 years ago
by
RAJAT99
Answered
I have used built in Vivado 2018.1 project (project_1.xpr) from this link https://support.xilinx.com/s/article/1072248 in to vivado ML edition(vitis2022.2). One error " [IP_Flow 19-993] Could not find IP file for IP 'axi_iic_0' " . How ca
0
1149
views
1
reply
Latest
over 2 years ago
by
flyingbean
Answered
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings
+1
1949
views
7
replies
Latest
over 2 years ago
by
canisio
Not Answered
Does changing RX lane rate between 300 and 600 Mbps change RX CSI-2 MIPI D-PHY IP topology (HDL code of soft IP)? Good Day Dear , In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which is tuned to receive CSI-2 traffic at 300 Mbps per la
0
538
views
2
replies
Latest
over 2 years ago
by
Annu16
Not Answered
How to program Axi SPI using Arty7 - 35T
0
1046
views
1
reply
Latest
over 2 years ago
by
jafoste4
Discussion
Maximizing Vivado Efficiency with Board Awareness
650
views
0
replies
Started
over 3 years ago
by
bhfletcher
Not Answered
Ultra 96 Xilinx ZYNQ UltraSCALE Software and Installation Support
0
908
views
1
reply
Latest
over 3 years ago
by
narrucmot
Not Answered
Petalinux 2021.2 and TFTP server address
0
1450
views
1
reply
Latest
over 3 years ago
by
jafoste4
Not Answered
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings error
0
773
views
0
replies
Started
over 3 years ago
by
masonhhh
Discussion
Issue with FIR Compiler V7.2 in RFSoC Design
1734
views
1
reply
Latest
over 3 years ago
by
PaulBray
Discussion
Vivado Boards List doesn't show ZedBoard
7231
views
4
replies
Latest
over 3 years ago
by
bhfletcher
Answered
Microzed development in EDK
0
1605
views
7
replies
Latest
over 3 years ago
by
bhfletcher
Suggested Answer
Xilinx Hello world on PicoZed 7020 SOM
0
1160
views
1
reply
Latest
over 5 years ago
by
bhfletcher
>
