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Threads
455 Questions
Frequently Asked
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings
Answered
2 months ago
Petalinux 2021.2 and TFTP server address
Not Answered
over 1 year ago
Ultra 96 Xilinx ZYNQ UltraSCALE Software and Installation Support
Not Answered
over 1 year ago
How to program Axi SPI using Arty7 - 35T
Not Answered
9 months ago
Does changing RX lane rate between 300 and 600 Mbps change RX CSI-2 MIPI D-PHY IP topology (HDL code of soft IP)? Good Day Dear , In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which...
Not Answered
7 months ago
Using Xilinx Tools Forum
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Tutorial 09 PL I2C PMOD from this link.
0
146
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0
replies
Started
4 days ago
by
RAJAT99
Answered
I have used built in Vivado 2018.1 project (project_1.xpr) from this link https://support.xilinx.com/s/article/1072248 in to vivado ML edition(vitis2022.2). One error " [IP_Flow 19-993] Could not find IP file for IP 'axi_iic_0' " . How ca
0
423
views
1
reply
Latest
11 days ago
by
flyingbean
Answered
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings
+1
892
views
7
replies
Latest
2 months ago
by
canisio
Not Answered
Does changing RX lane rate between 300 and 600 Mbps change RX CSI-2 MIPI D-PHY IP topology (HDL code of soft IP)? Good Day Dear , In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which is tuned to receive CSI-2 traffic at 300 Mbps per la
0
197
views
2
replies
Latest
7 months ago
by
Annu16
Not Answered
How to program Axi SPI using Arty7 - 35T
0
388
views
1
reply
Latest
9 months ago
by
jafoste4
Discussion
Maximizing Vivado Efficiency with Board Awareness
428
views
0
replies
Started
11 months ago
by
bhfletcher
Not Answered
Ultra 96 Xilinx ZYNQ UltraSCALE Software and Installation Support
0
603
views
1
reply
Latest
over 1 year ago
by
narrucmot
Not Answered
Petalinux 2021.2 and TFTP server address
0
821
views
1
reply
Latest
over 1 year ago
by
jafoste4
Not Answered
AVNET Xilinx RFSoC Gen1 Kit for LTE: Invalid Mixer mode in XRFdc_SetMixerSettings error
0
525
views
0
replies
Started
over 1 year ago
by
masonhhh
Discussion
Issue with FIR Compiler V7.2 in RFSoC Design
759
views
1
reply
Latest
over 1 year ago
by
PaulBray
Discussion
Vivado Boards List doesn't show ZedBoard
3108
views
4
replies
Latest
over 1 year ago
by
bhfletcher
Answered
Microzed development in EDK
0
767
views
7
replies
Latest
over 1 year ago
by
bhfletcher
Suggested Answer
Xilinx Hello world on PicoZed 7020 SOM
0
538
views
1
reply
Latest
over 2 years ago
by
bhfletcher
Answered
Modifying SDK to Use a Generic Hyperterminal
0
438
views
4
replies
Latest
over 3 years ago
by
arneldcollins
Discussion
PCIE Lane Change from GT Lane 0 Vivado
456
views
0
replies
Started
over 4 years ago
by
denyss
Not Answered
Error building OOB Design in ISE 14.4
0
363
views
2
replies
Latest
over 4 years ago
by
bent9
Not Answered
Cannot include .hpp file in Vivado HLS (using OpenCV)
0
1064
views
2
replies
Latest
over 4 years ago
by
kotrasharmila
Not Answered
Can't access FPGA registers from my Standalone app
0
273
views
1
reply
Latest
over 4 years ago
by
bhfletcher
Not Answered
Booting picozed with FreeRTOS app
0
369
views
4
replies
Latest
over 4 years ago
by
Former Member
Not Answered
Do I need to specificy that an app starts from the FSBL?
0
245
views
1
reply
Latest
over 4 years ago
by
Former Member
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