Hello,
after opening "Microzed Base IOCC" project in Vivado 2014.4 and validating it, following warnings produced:
[BD 41-1348] Reset pin /axi_gpio_0/s_axi_aresetn (associated clock /axi_gpio_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET0_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
After ignoring them, synthesis succeeded and timing constraints are met.
Should I follow that warnings and add Processor System Reset? Is there guide how to setup it properly?
