Calling out to the community in hopes someone has seen this and knows the problem.
i have my app converted over to standalone, moving from the socket model to the tcp model (raw?), but I have a major problem in that anytime I try to access the FPGA registers the network seems to hang, or the app. I suspect there's memory contention between the network and the addresses, but don't know that for fact. I know that once I access an address to read/write I can't send any data over the ethernet and I will get a network timeout in my putty session promptly after.
This worked fine on the FreeRTOS app, but the difference is that the network model is different.
Do I need to restrict my FPGA locations?
base address is 0x43C00000 and I'm only trying to access at the 0 offset, which is a scratch register.
i like the socket model better, as the FreeRTOS example uses, opposed to the tcp model (raw?) which the Standalone uses.
I don't know if I would be better over on the Xilinx forums or not.