Vivado HLS synthesize while loop

Question

Hi everyone

Recently, I am using Vivado HLS to complete my design based on Zedboard. In my design, I use a while loop, However I have never learnt some introductions of Vivado HLS about while loop, many of them are related to FOR loop. So I want to know whether Vivado HLS can systhesize while loop? Does it have some disadvantages? or other methods to solve this problems.

Thanks for reply!

jafoste4 · Answer

Hello Yinxh, Here is a good place for you to start looking https://forums.xilinx.com/t5/General-Technical-Discussion/problem-in-while-loop-in-VHDL/td-p/82961 --Josh