Hello Xilinx Community,
I am trying to design a Network tap using the Avnet Zedboard (Zynq 7000) and the Ethernet FMC. The goal is to be able to monitor Ethernet traffic and chose whether or not to pass certain frames through the link, based on arbitrary information within the packet itself.
IMPT: I am trying to have the packet inspection done entirely in hardware, as the processor is meant to be running other time-sensitive applications.
Currently, I have two AXI Ethernet subsystems tied together in promiscuous mode, and wired to external ports on the FMC. Ideally, the packet would be processed by one of the Ethernet Subsystems, and fed into the other system for transmission if external logic deems the packet valid.
Problem: I cannot figure out how to configure the TEMACs without using the processor. I saw that they have a "non-processor mode" but the manual states it is for use in 1000-BaseTX systems only. Is there a way to bring up the Ethernet Subsystems in my design without the processor writing to the configuration registers over AXI4-Lite on the s_axi bus?
Also, if somebody believes this is not the best way to implement a network tap, please let me know. I chose two use the Ethernet Subsystem IP blocks because they recognize the concept of an ethernet "frame" and wouldn't require me to have to assemble a frame manually. If this seems inefficient, I'm all ears for other ideas.
Thanks in advance!
Brett
