Hi,
I am trying to design sliding leds ( a single LED flash enough any time) on Zed Board. I wrote an assembly code, created a top level verilog file and a constraint file but it did not work.
I am familiar with assembly but I have no experince on assignment of I/O. I have an example project which blinks a single LED. I modified it to flash all 8 leds on the board but I could not.
Can someone help me?
In vivado I could not generate bit stream because it gave pin planning erros.
Can someone help me?
Basicly ther will be no input rather than clock, the output will be 8 general purpose leds. (T22, T21, U22, U21, V22, W22, U19, U14)
my .xdc file and error is below:
---------------------------------------------
#IO_L11P_T1_SRCC_35
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk]
#IO_L20N_T3_34
set_property PACKAGE_PIN N15 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
#IO_L23P_T3_35
set_property PACKAGE_PIN T22 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN T21 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN U22 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN U21 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN V22 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN W22 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN U19 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property PACKAGE_PIN U14 [get_ports led_out]
----------------------------------------------
- Pin Planning
- [DRC NSTD-1] Unspecified I/O Standard: 32 out of 33 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: address[11:0], instruction[17:0], enable, and rdl.
- [DRC UCIO-1] Unconstrained Logical Port: 32 out of 33 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: address[11:0], instruction[17:0], enable, and rdl.