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7z020 XDC file

Former Member

Hello,

I'm trying to get used to the microZed board with the I/O carrier board using Vivado 2013.3.
As "hello_world" I want to use the user push buttons to toggle the user leds on the carrier board.

Due to the fact that the microZed board device from the Vivado project wizard is the "xc7z010clg400-1", but my Zynq says XC7Z020, I choose the "ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1)" as poject device.

I have a block design with the zynq, axi interconnect and two axi gpio blocks. one gpio block as input and one as output for the leds.

My microZed Zynq is a XC7Z020, so I'm downloaded the "MicroZed Master XDC Rev B v1" and choose the "microzed_7z020_master_XDC_RevB_v1.xdc" as constraint file.
As the signal names are from the microZed schematic and not the carrier board schematic I named my ports "JX2_LVDS_16_P" and so on.
In the XDC file I changed the IOSTANDAD voltage from LVCMOS18 to LVCMOS33.

________________________________________
Now to my Problem:

I get the error DRC 23-20: rule violation (NSTD-1) unspecified I/O Standard.
http://www.xilinx.com/support/answers/56354.html
As I understand xilinx just explains the error code and that my XDC file is wrong.

Can anyone explain to me what's wrong here:

...
# Bank 34, Vcco = Vadj
# Set the bank voltage for bank 34.
set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 34 } ]

set_property PACKAGE_PIN T10 [get_ports {JX1_LVDS_0_N}]
set_property PACKAGE_PIN T11 [get_ports {JX1_LVDS_0_P}]
...

I only changed the LVCMOS33 from LVCMOS18 as mentioned earlier.

I have three suggestions what can maybe wrong: the XDC, the Project device or my Zynq is just an XC7Z010 and not a XC7Z020 as it says on the package....

Thanks for any help and suggestions
Regards
David

  • 0

    Hi David,

    I believe what you are talking about is that you have a MicroZed 7020 instead of the basic MicroZed 7010, right?

    If that is the case, you will not be able to use any of the board definitions built into Vivado 2013.3 to select the device.  Instead you will need to manually select the xc7z020clg400-1 device which is populated on the MicroZed 7020 SOM.  You have incorrectly selected the 7020 device from ZedBoard which is a 484 pin package so the package-to-pin mapping will not match what is physically placed on your MicroZed 7020 module since the xc7z020clg400-1 device is a 400 pin package of the same 7020 Zynq device.

    If you read the tiny letters on the top of the Zynq package (you might need an eye loupe to do so) and it says 7020, then it is a 7020 since I don't think we have enver seen any incorrectly labeled Zynq devices.

    Regarding the XDC file, I have run into similar issues when building reference designs.  Although the XDC format we publish for MicroZed is based upon what Xilinx publishes for ZedBoard, I found that (at least Vivado 2013.3 does) an XDC constraint to set I/O properties on multiple pins by filtering on the bank property does not seem to work well.  I have found that separate constraints for each pin seems to work okay.

    Try assigning the IO standard to each pin separately instead:

    set_property PACKAGE_PIN T10 [get_ports {JX1_LVDS_0_N}]
    set_property PACKAGE_PIN T11 [get_ports {JX1_LVDS_0_P}]

    set_property IOSTANDARD LVCMOS33 [get_ports {JX1_LVDS_0_N}]
    set_property IOSTANDARD LVCMOS33 [get_ports {JX1_LVDS_0_P}]

    That usually works for me, let us know if it works for you as well.

    Regards,

    -Kevin

  • 0 in reply to zedhed

    Hi Kevin,

    thank you very much.

    As the ZedBoard is configured with the 484 pin package I thought the 7z020 Zynq needs more pins because it has the Bank13. Now a close look on the package confirms it's the 400 pin package.

    This issue with the XDC file is inconvenient, but thanks. It seems to work. :)

  • 0

    Hi David,

    I don't know if this will help you at all but perhaps it will be useful to others reading this.  I happened to stumble across this the other night.  If I place the following IOSTANDARD constraints within my XDC file AFTER all of the PACKAGE_PIN constraints are listed then it appears I can assign the IOSTANDARD across all of the pins that have been assigned within those IO banks without having to assign the IOSTANDARD individually to each port as I mentioned above.

    set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
    set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];

    Keep in mind that this might not work well if you are using multiple XDC constraints in your design unless you can be certain that all PACKAGE_PIN constraints are evaluated prior to the IOSTANDARD constraint evaluation.

    Regards,

    -Kevin

  • 0

    I am unable to see signal behavior on led , as i am using zedboard so there are some dedicated pins for LED.

    Even before that i wanted to see output signals on zedboard pmod pins but i did not get on pmod pins.

  • 0

    Master ucf/xdc does not contain enet pins? Where can I find a complete pinout for Zedboard?

  • 0 in reply to Former Member

    Both the ZedBoard schematic and Hardware User's Guide, which has tables of pin assignments, are available to download here:

     

    http://microzed.org/support/documentation/1521

     

    The master ucf/xdc files do not contain pins previously defined by the board preset.

     

    -Gary