PS/PL BRAM share

Would using the AXI4 MMAP interface for the custom accelerator provide the functionality that I am looking for? On the surface, the documentation seems to indicate its use more for data peripherals than for parallel number-crunching, but actually i have not seen reference designs.

added to my ip .mpd file (from axi_bram_ctrl .mpd):

BUS_INTERFACE BUS = BRAM_PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = INITIATOR


and
PORT BRAM_Rst_B = BRAM_Rst, DIR = O, BUS = BRAM_PORTB
PORT BRAM_Clk_B = BRAM_Clk, DIR = O, BUS = BRAM_PORTB
PORT BRAM_En_B = BRAM_En, DIR = O, BUS = BRAM_PORTB
PORT BRAM_WEN_B = BRAM_WEN, DIR = O, BUS = BRAM_PORTB,  VEC = 3:0, ENDIAN = LITTLE
PORT BRAM_Addr_B = BRAM_Addr, DIR = O, BUS = BRAM_PORTB, VEC = [(C_S_AXI_ADDR_WIDTH - 1) : 0], ENDIAN = LITTLE
PORT BRAM_Dout_B = BRAM_Dout, DIR = O, BUS = BRAM_PORTB, VEC = 31:0, ENDIAN = LITTLE
PORT BRAM_Din_B = BRAM_Din, DIR = I, BUS = BRAM_PORTB,  VEC = 31:0, ENDIAN = LITTLE


now it looks pretty in XPS.

now to make sure my HDL matches!

Hurray! The HDL (from PlanAhead) is synthesizable.
Getting it right in the pcore put it right automatically, and the XPS Bus Interface tab looks clean.

"We don't need no stinkin' XPS license."

So now, do the DMA from FreeRTOS, and then roll the BRAM data to my submodule ports.
Getting there. Can I do it?

Hello james,

I'm working on this issue. I instantiated a BRAM controller and a BRAM in my XPS project, but when I push the "Generate Addresses" button, then the controller remains under the "Unmapped addresses" list. It gets an address, but it seems that is unmapped. I followed UG873 cap.6 to instantiate a CDMA peripheral. Could you give me any hints to solve my problem?

Thank you,
sticken

Hi,

I got the same result -- the bram_ctrl remained under unmapped but received an address. This address is used to access the BRAM from the CDMA. I was able to use this address to execute DMA transfers to and from BRAM to and from high OCM.
did you try to complete the SDK app and attempt a DMA transfer?
In another vein, for my attempted accelerator, I used the ACP to move datasets into BRAM instantiated in XPS. But then I got bogged down when trying to access the BRAM from within my custom IP user logic. The resultant dual bus AXI and BRAM interface module is giving me problems where the user_logic modules are trimmed in synthesis due to the way the BRAM access is coded in HDL. I needed to add the BRAM interface to my IP's .mpd. XST is somehow setting the BRAM ports to constant values and trimming the module.
So I changed to the AXI burst mode in the CIPW and now am working with that mode of transferring the dataset. This creates inferrred BRAM within the IP user_logic, which you can use to transfer data sets and results. However, I don't think the burst mode is supported in AXI_Lite, so I think you need to convert your XPS design to AXI from AXI_lite.
I still work on both versions though. I can't see why you can't access the BRAM from your IP and am reading the 400+ pages of HDL for the AXI_BRAM_CTRL Xilinx IP to get insights into how to have AXI and BRAM bus interfaces in coexistence.

hope this helps.

i think avnet and/or xilinx neds to weigh in on this subject with reference designs, UG etc.

Thank you for your quick answer. You're right, it seems that DMA transfer from DDR to BRAM ends succesfully: status register contains correct value. But I can't understand one thing. BRAM controller is automatically connected to a BRAM in PL? I tried to perform another transfer, from BRAM controller to DDR in order to check whether the values are correct, but they're not..maybe I missed something..

Thank you again,
sticken

I am also trying to use PL as an accelerator and need a shared buffer for communication between PL and PS. It seems that the AXI_BRAM_CTRL might be helpful. According to the posts "Can the AXI BRAM CONTROLLER ports be made external", it should be able to have a BRAM port exposed to user logic. However, I tried all the possible configurations, and now I am pretty sure there is no way I can make any of the BRAM port external at least on XPS 14.4. I am not sure if it a bug or something. Anyway, I also tried another way by adding an AXI4 peripheral with the XPS wizard. By default, I got an AXI4 peripheral supporting burst transfer. The default configuration of the peripheral is actually a RAM block implemented in synthesizable HDL code. It is really cool, because it allows me to configure the BRAM whatever I want. While the problem is that it does not support AXI burst and I am not familiar with AXI4 protocol. So I am writing to see if I missed something. I guess this is really a basic communication scheme for PL and PS. Is there any easier way to implement a dual port BRAM for the PL-PS communication? If not, I may have to go back to the lengthy AXI4 specification.

I want to know how you can solve the problem,can you tell me the way and give me the source code you write,thank you

Finally I managed to perform a DMA transfer from DDR to BRAM and from BRAM to DDR. Unfortunately when I read value wrote back in the DDR I face a strange behaviour. In practice some values don't make any sense to me. The CDMA transfers number from 0 to 1023 (so 1024 integers, each of them 32 bit wide). Ok, when I print the numbers stored in the destination memory I see that some values don't belong to numbers from 0 to 1023.

Example:

Value: 892
Value: 893
Value: 894
Value: 895
Value: -476021416
Value: 27279365
.
.
.
Value: 912
Value: 913
Value: 914

As you can see the is an interval of numbers that are completely wrong. Strange behvior: those intervals can be more than one and I noted that are made by 8, 16 or 32 numbers..

Any hint would be really appreciated!!

sticken

My design only used OCM and not DDR. Sorry and good luck finding it.
Probably an issue specific to using DDR with CDMA. If I find the answer digging into the TRM, I will post it here.