Actions
Forum Thread Details
  • State Not Answered
  • Replies 4 replies
  • Subscribers 335 subscribers
  • Views 816 views
  • Users 0 members are here
Related

Vivado HDMI reference design

Former Member

Xilinx Vivado Design Suite 2013.2 is out, with Zynq support for IP Integrator.
I was successful with the basic tutorial (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug940-vivado-tutorial-embedded-design.pdf), I've created a sample LED blinking project.
Unfortunately, I am stuck with the HDMI output controller. I've imported the EDK HDMI cores (axi_clkgen, axi_hdmi_tx_16b), but I am unsure what to do next, which interface should I connect to where, etc.
For example: the XPS Linux reference design (http://digilentinc.com/Data/Products/ZEDBOARD/ZedBoard_Linux_Design.zip) connects the M_AXIS_MM2S interface of the VDMA with the M_AXIS_MM2S interface of the HDMI_TX. Vivado does not allow this connection. Also, the Vivado VDMA core does not have the mm2s_fsync_out wire, so I can't connect it to vdma_fs_ret in the HDMI core.

My question is: is there a ZedBoard reference design for Vivado, or a step-by-step guide to create a HDMI output design (in XPS) so that I can be sure that I am doing the right thing?

Regards,
Gabor

  • 0

    I'd like to second this request. Its frustrating that everyone suggests moving to Vivado rather than XPS/PlanAhead with new designs, but there are none of the custom sources and not half as many tutorials.

  • 0

    Hi Gabor,
    I'm also working on a port of AD's reference design cf_adv7511_zed to Vivado. I also couldn't find it online and decided to create it myself based on the existing design for ISE-XPS.
    While doing that I ran into the same two problems you mentioned and this is how you can get around it:

    1. M_AXIS_MM2S interface: when you package up axi_hdmi_tx_v1_0 it automatically chooses port m_axis_mm2s to be a master port based on the M_ prefix. However, when you look at the individual port directions (e.g. m_axis_mm2s_tdata is input just like in a slave interface) this interface is clearly an axi_stream_slave interface and not a master. I don't understand why they called it M_AXIS_MM2S and not S_AXIS_MM2S. In IPI you can manually change the m_axis_mm2s inferface to slave in the 'IP Interfaces' section. After that is done you can connect it to the VDMA core just like in the reference design.

    2. The mm2s_fsync signal is a hidden port in the VDMA core and you can re-enable it with the TCL command:
    set_property -name {CONFIG.C_ENABLE_DEBUG_INFO_1} -value {0} -objects [get_bd_cells axi_vdma_0]
    For further reading you can refer to Xilinx VDMA design guide at http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_0/pg020_axi_vdma.pdf

    Regards,
    - Arnd

  • 0

    Hello Gabor,
    Have you succeeded with HDMI controller in Vivado.
    If yes can you kindly guide me?
    I implemented the basic led blinking for zedboard and understood about the u-boot.

    Now i want to implement a basic HDMI project and draw some basic shapes like (circle, triangle etc).

    Regards
    Hamid

  • 0 in reply to Former Member

    Thank you so much for this post. It got me unstuck!

    By the way, if anyone reading this is using the AD-FMCOMMS1 design with Zedboard under Vivado, it looks like Analog Devices is about to re-release its reference design which will be done using Vivado and IP Integrator. A date of 3/17 was given so we'll see.

    Here's the relevant link at AD's site. You may need to create a dummy account to access it.

    http://ez.analog.com/thread/40069