EDK DRC problems with default clock settings

Hi,

I am trying to follow the tutorial at http://zynqgeek.blogspot.it/2012/08/zedboard-create-planahead-project-with.html

In XPS, after loading the XML board configuration file, DRC completes with no errors.

Back into PlanAhead, I create the top HDL and run the synthesis.

I get a message box with the following message:

<<
DRC check found issues in the design. Please see the console log for more details.
>>

The TCL console reads:

<<
ERROR:EDK - issued from TCL procedure "zynqconfig_do" line 34
   processing_system7_0 (processing_system7) - MHS file editing for Zynq related
   parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
    Value of parameter C_FCLK_CLK0_FREQ (96461533) in MHS conflicts with the
   setting in Zynq tab. Value of C_FCLK_CLK0_FREQ should be 100000000
>>

This message disappears if I modify the input clock frequency in XPS (in the "Zynq" tab, "Clock Generation" block, "Zynq crystal" set to 35 MHz instead of 33.33 MHz) and run the synthesis again.

I am using ISE 14.2 for Linux.

Did anyone experience the same problem?

Guillaume Savaton

0 Former Member over 12 years ago

gsavaton,

What version of the XML did you import into XPS? Was it the current version from this link:

http://zedboard.org/sites/default/files/documentations/zedboard_RevC_v2_XML.zip

Did you follow the how-to that ZynqGeek posted step-by-step?

It looks like something along the way, perhaps a tcl script, is calculating the wrong clock frequency for the PS. Can you post your MHS file? I suggest using pastebin.org.
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0 gsavaton over 12 years ago in reply to Former Member

> What version of the XML did you import into XPS? Was it the current version from this link:

Yes, I used the RevC v2 XML.

> Did you follow the how-to that ZynqGeek posted step-by-step?

I think so.

I also tried to start a project without selecting any board, and added the processing system manually in XPS.

I got exactly the same result.

> Can you post your MHS file?

Here it is:
http://pastebin.com/GPTvS2u7

It contains this line:
PARAMETER C_FCLK_CLK0_FREQ = 96461533
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0 Former Member over 12 years ago in reply to gsavaton

gsavato,

If you change that line from 96461533 to 100000000 does it work?
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0 gsavaton over 12 years ago in reply to Former Member

Yes.

I have to change all clock frequency settings, from CLK0 to CLK3, to match the expected frequencies.
Then synthesis completes with the usual warnings, and I can proceed to implementation and bitstream generation.
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0 Former Member over 12 years ago in reply to gsavaton

i had the same problem as i used an 13.4 lincense file for my ISE 14.2. As i moved to the license Server of my University all clock problems where gone.
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0 Former Member over 12 years ago

I had the same problem under linux, but its gone when I unset locales:
unset LANG
unset LC_ALL

I have both commands now in my settings64.sh.

Credits to http://www.zedboard.org/content/ise-142-bug-reports
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0 Former Member over 12 years ago in reply to Former Member

I had Swedish locale (Ubuntu 12.04-64bit) and here the decimal sign is the "comma". The "Clock Wizard" scripts do however calculate with the "dot". Meaning that 33,333333MHz will be truncated to 33MHz as input frequency.
I run 14.4 version.

In my settings64.sh I override all my Swedish locale with:
export LC_ALL=en_US.UTF-8
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0 Former Member over 12 years ago

Hey
When I launch generate bitstream I have this messages.
[Edk 24-135] DRC check found issues in the design. Please see the console log for more details.

[HDLCompiler 1654] Instantiating <system_i> from unknown module <system> ["/home/eukrea/Documents/silica/tutoriel/fpga/lab4/LED_Controller/LED_Controller.srcs/sources_1/edk/system/system_stub.v":60]

I don't know where is the problem

I added
unset LANG
unset LC_ALL

unfortunately it des'nt worK.
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0 Former Member over 12 years ago

hey when I create embedded and I add the processor arm processing system when I generate netlist I had this error whereas I add only the processor Do you can help me ?
Cordially.
processing_system7_0 (processing_system7) - MHS file editing for Zynq related
   parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
    Value of parameter C_FCLK_CLK0_FREQ (49500000) in MHS conflicts with the
   setting in Zynq tab. Value of C_FCLK_CLK0_FREQ should be 50000000
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0 Former Member over 12 years ago

I test the manipulation with the version 14.2 I had'nt this problem.
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