Hi all,
I have a general question: is there any document explaining how to achieve multi-port memory access (like MPMC on Spartan 6) ?
Thanks!
Hi all,
I have a general question: is there any document explaining how to achieve multi-port memory access (like MPMC on Spartan 6) ?
Thanks!
Hi lin.zhang,
Since MPMC was a hardware block on Spartan 6 and the Series 7 devices do not have these dedicated resources, your best luck will probably be with using the Memory Interface Generator (MIG) to implement another memory interface from the PL side.
Although it is not clear when this will be supported in the tools, there has been some mention of the possibility of doing this. Take a look at this Xilinx thread for more information:
http://forums.xilinx.com/t5/Embedded-Processors-and/Zynq-DDR-controller-at-the-PL-s-site/td-p/290473
Regards,
-Kevin