OK, I am primarily a software engineer picking up Verilog programming. In software, I like to parameterize "magic numbers" like AXI Cache definitions, Lock values, field sizes, etc to avoid problems later with mismatches. I like to put these generic constants in a separate header file that can be consistently included across every project.
Now to my problem. Everything I have tried (`define, parameter, localparam) has given me syntax errors:
Header file:
`define C_AXI_AxBURST_SIZE_WIDTH 3
`define C_AXI_AxBURST_SIZE_1 C_AXI_AxBURST_SIZE_WIDTH'b000t// 1 byte wide
Main body:
Module Xxx
#(...
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h4000_0000,
...
)
(
...
)
I get syntax errors at the constant definitions after the ' character.
I know it's something simple. Can anyone spot what I'm doing wrong?
