Hi,
Can the microZed constraints file be found somewhere?
I'm looking for the timing constraints.
Does anyone know where to find them?
-cja
Hi,
Can the microZed constraints file be found somewhere?
I'm looking for the timing constraints.
Does anyone know where to find them?
-cja
Hi,
The only provided file is a pin map XDC. The timing constraints are provided by the user once you decide what clocks you are using.
If you want to see the constraints that the design is using (Vivado will assume some things based on clocks), you can use the write_xdc command:
write_xdc c:/my_output_test.xdc
In there, you will get a compiled list of all the constraints the current project is using. Remember, in XDC if there is a conflict, the last constraint is the one that is implemented.
--Dan
As a follow up to this.
To create accurate constraints, one must know the time delay of signals traveling to/from the FPGA chip to the external devices (chips) that you are interfacing to. As engineers, we are responsible for the delay from the BERG connector to the external chip. However I need to know the delays from the FPGA chip to the BERG connectors in order to complete the constraints.
Can you point me to a table of delay times for each of the IO signals?
Cheers,
David
Hi David,
You can generate those yourself using Vivado. Please refer to this post and modify it for the package you are using.
http://zedboard.org/content/picozed-7020-package-flight-times
--Josh
Hi there,
You can find the trace length report here:
http://picozed.org/support/documentation/4736
Search: "net length"
Using that, you can calculate the delay times for your circuit. Remember that we do not have a time-table, as the tolerance and specific constraints you write will be based on what you are doing with the signals you are using. Knowing the net lengths will allow you to add in the internal delays (as Josh mentioned, come from Vivado), plus add in any delays with your Carrier Card, to finally come up with your constraint.
UG612 might be of some help to you.
https://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf
--Dan