Hi,
I am facing problem in driving fsync in signal in VTC ip.
what signal from Video in to axi out ip will drive this signal and what this signal signify.
and same how to utilize fsync_out and why it has some width.
what is it signify.
Hi,
I am facing problem in driving fsync in signal in VTC ip.
what signal from Video in to axi out ip will drive this signal and what this signal signify.
and same how to utilize fsync_out and why it has some width.
what is it signify.
Hi rajee_var,
Is this related to the Video Timing Controller IP from Xilinx?
If so, this is a Xilinx support issue, I suggest you also open a Xilinx WebCase in parallel with this forum posting.
www.xilinx.com/webcase
Regards,
-Kevin