Hello,
i want to create the BOOT.BIN file for a ZedBoard with one AXI UART LITE interface in the PL. The file is created with no error messages but does not work. I'm using the PlanAhead version 14.6.
My workmate tried to generate the BOOT.BIN file with the PlanAhead version 14.4 and it works. Is this an error in the newer version of PlanAhead or did i make something wrong?
Line of action:
- PlanAhead 14.6
New Project...
RTL Project
Target language: VHDL (no sources added)
(no IPs added)
(no contraints added)
Default Part: ZedBoard
Finish
Add Sources...
Create Embedded Sources
Create Subdesign (name: system)
Finish
- XPS
Pop-up: Add processing system 7 ? Yes!
Import... ZedBoard Development Board Template
Add IP: AXI UART (Lite), connect with processing_system7_0
connect with interrupt controller
close XPS
- back in PlanAhead 14.6
Add Sources... Create Constraints
Create File... ser_schnittstelle.ucf
> # ser_schnittstelle.ucf
> NET "axi_uartlite_0_RX_pin" IOSTANDARD=LVCMOS25;
> NET "axi_uartlite_0_TX_pin" IOSTANDARD=LVCMOS25;
> NET "axi_uartlite_0_RX_pin" LOC=V10;
> NET "axi_uartlite_0_TX_pin" LOC=W8;
Create Top HDL
Generate Bitstream
Open Implemented Design
Export Hardware for SDK... (all boxes checked)
- SDK
Project -> check box: Build Automatically
File -> New -> Application project (name: fsbl)
Target Hardware: system_hw_platform
Processor: ps7_cortexa9_0
OS Plattform: standalone
Next -> Zynq FSBL -> Finish
Modify BSP Settings
Standalone -> stdin: ps7_uart_1, stdout: ps7_uart_1
Xilinx Tools -> Create Zynq Boot Image
List of Partitions: fsbl.elf, system.bit
Add... u-boot.elf
Create Image
rename to BOOT.BIN
Thank you for your time!