Vivado custom VHDL/Verilog block

Hi,

In vivado, I would like to create a vhdl block in my design. I know how to create a custom AXI IP, but I didn't find a solution to create a custom VHDL block. Is there a solution to create it ?

Regards,

Snoopy

0 Former Member over 11 years ago

Look at the Xilinx Vivado "Design Suite Users Guide - Designing with IP" (UG896) for details: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug896-vivado-ip.pdf

In summary what you will do is open Vivado and select the device (Zynq I assume) that you want to target and either add an existing HDL file or create a new one. Once you are happy with the operation of the HDL block then you can go up to 'Tools' on the Vivado tool bar and select 'Create and Package IP'. Then follow the steps to package your current project as an IP. Once this is complete you will need to add the directory this project is in to a repository visible to your top level project. Then your new custom HDL module will appear as one of the IP selections in the IP Integrator.

-Gary
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0 Former Member over 11 years ago

Hi Gary,

Thanks for the response.
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0 Former Member over 11 years ago

Hi

Am new to Vivado pls can anyone help me to create a custom IP using verilog with an example.

Regards
Govind Raj
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0 Former Member over 11 years ago

The lab material in the Avnet Developing Zynq-7000 All Programmable SoC Hardware (Vivado 2013.3) Speedway Design seminar includes an example creating custom IP using Verilog. You can download the Speedway material here:

http://zedboard.org/support/trainings-and-videos

-Gary
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