LVDS Clock Input Buffer

Not sure if this is the right forum, but......

I want to bring a LVDS clock into the MicroZed board and feed it into a (as a CLOCK) "Clocking Wizard" IP block as well as a "SelectIO Interface Wizard" (as DATA) IP block.

I can't directly connect each block input to the pins, so I need to connect the LVDS clock through a buffer and then fan out from there. The only block I can find is the "Utility Buffer" which has a bunch of options, but I don't know which one to select.

0 zedhed over 9 years ago

Hi craig_lindholm,

You might get a better answer from the Xilinx forums since your question relates more to the FPGA logic of their Zynq-7000 device. However, I do have an answer for you (the same answer given to me many years ago) and that is "it depends on what you are doing with the clock once it's in the FPGA".

Check out Xilinx UG472, specifically Chapter 2 in the section titled "Clock Buffer Selection Considerations" for details on how the different clock buffer options work and why you might choose one over another:

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Regards,

-Kevin
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