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Problem in generating a 4 MHz Clock using Microzed.

Former Member

Hi All,

  I am trying to generate a 4 MHz clock using the Microzed Board. I am using the PL Fabric IO PLL set to 4 MHz, but I get an output of approximately 100 MHz.
  I used LEDs to checkt the output frequency.

VHDL Code ----------------------------------------
testClkProcess: process
    variable count: integer range 0 to 99_999_999 := 0;
begin
    wait until rising_edge(clk4);
    if count = 99_999_999 then
        count := 0;
        sLeds(5) <= not sLeds(5);
    else
        count := count + 1;
    end if;
end process;
--------------------------------------------------

According to the above code, the LEDs should blink every 25 seconds by using clk4 but they blink approximately at 1 second.

I stumbled on this issue while working on a more complicated project and finally debugged the issue to not being able to generate a 4MHz clock, instead 100 MHz clock instead being used for the same!

  I have tested the same code in ZedBoard and it works fine. But MicrozedBoard seems to have this issue.

Thanks,
Wasim

  • 0

    Hi,

    I do not think the above code going to synthesize into hardware in the way you think.  I believe that the wait until is only applicable in simulation.  Remember, in true hardware, the wait until, the if/else are all executed at the same time.

    Try:

    COUNTER_PROCESS: process(reset, clk)
    begin
       if(reset = '1') then
          countt<= (others=>'0');
       elsif(rising_edge(clk)) then
          if count = 99_999_999 then
             count := 0;
             sLeds(5) <= not sLeds(5);
          else
             count := count + 1;
       end if;
    end process;

    You will need to check the above for syntax.

    Personally, I like to work in STD_LOGIC or UNSIGNED.  Personal preference.  I think all the syntax is correct on this one:

    COUNTER_PROCESS: process(reset, clk)
    begin
       if(reset = '1') then
          countt<= (others=>'0');
       elsif(rising_edge(clk)) then
          if (count = #"5F5E0FF") then
             count <= (others=>'0');
             sLeds(5) <= not sLeds(5);
          else
             count <= std_logic_vector(unsigned(count) + 1);
       end if;
    end process;

  • 0

    FYI, looks like you will need to change where I put clk to clk4.
    Also, I personally have not written an integer like that.  I know that _ is a concatenate in VHDL, so interesting that you put that in there in place of a ",".