Hello all,
I have been working with Xillybus in my Zedboard.
Now I have been trying to generate some IP with Vivado HLS, but I have faced a problem everytime I operate with float numbers.
The HLS process works fine but when I use the ISE to synthetize the project and add the .v sources I always get the error with one or several of the next modules
myproject_ap_fmul_2_max_dsp_32_u
myproject_ap_fadd_3_full_dsp_32_u
myproject_ap_fsub_3_full_dsp_32_u
myproject_ap_fsqrt_10_no_dsp_32_u
The same happens when using the vh files.
"fmul" I guess is "float multiplication", "fadd", "fsub" and "fsqrt" I guess are add, substraction and square root of floating point numbers.
Along with the HDL files I can see that tcl files with names very close to missing modules were generated. For expample I got files like this:
myproject_ap_fmul_2_max_dsp_32_ip.tcl
I think that this tcl file would help me to synthetize the project somehow, but I do not really now.
Any idea on how to proceed. Really apreciate any advice.
