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Program only vhdl code on QSPI with iMPACT

Former Member

Hi,
I need to use my Zedboard for a very simple hardware project. So I don't need to use linux/ps. Only vhdl code to implement an analogic signal routing.
Of course I need to save the project (i.e. the bit file) on the board in order to have the same job done every time I turn on the Zedboard.
I've tried to program the QSPI through iMPACT (256M SPI with .mcs file) but I get a warning (The 'Data Width' you assigned is x0 but the PROM file (.mcs) is generated in a x8 mode. Please double check your assignments or it may not work properly. Click 'Yes' to ignore the conflict and proceed. Click 'No' to go back to the dialog).
I can still program the QSPI but after that, the Zedboard doesn't do what it's described in the
bit file (rather doesn't do anything at all!). If I just program the FPGA (no PROM/QSPI programming)
with the bit file, that works just fine so I'm sure that the bit file and the vhdl code are correct.

I would like to know if this is just an error of mine (then I'll appreciate any help!) or if I necessarily
have to use linux/ps (and so SDK for programming the QSPI) in order to save my project on the Zedboard.

I apologize if this is a stupid question but I had just switch to the Zedboard from Virtex-5 and so I
have some difficulties understanding the "FPGA with ARM" system since the PROM programming in the Virtex world was quite simple.

Thank you.

  • 0

    You will not need to use Linux, or any other application code, but you will need to use the PS. When the Zynq device powers up the PS section (the ARM core) is intiialized and then, based on the configuration inputs (jumpers on the Zedboard) it will load the PL bit stream from the selected non-volatile memory. On the ZedBoard you can boot/load from either the QSPI Flash or the SD card.

     

    So you will need to build a Zynq block design with the Zynq processor and at least a QSPI or SD card interface, along with your VHDL design. Once you implement this design and export it to SDK you can use the SDK to generate a First Stage Boot Loader (FSBL). You will need to have at least a zynq_fsbl_0.elf file to initialize the PS and a system.bit file that contains your PL bit stream. You can also have an additional .elf file containing an application to run on the ARM processor if you like, but it is not required that you use the Zynq processor for anything after loading the PL bit stream. You can program the QSPI Flash from the SDK.

     

    There are several tutorials out there you can look at to get started. If you have the chance the Avnet Speedway design workshops on the Zynq hardware and software are a great way to get started: http://www.em.avnet.com/en-us/design/trainingandevents/Pages/Xilinx-SpeedWay-Design-Workshops.aspx

     

    Otherwise, if you are using the ISE/PlanAhead tools take a look at the ZedBoard Configuration and Booting Guide as an example. It is from an earlier version of the ISE tools but should be applicable: http://zedboard.org/design/1521/11

     

    I you are using the Vivado tool suite take a look at the Tutorial 4 for the MicroZed board here: http://zedboard.org/design/1519/10

    While it is for the MicroZed board it will take you through the steps to generate the FSBL you need. We ahre having some issues with downloading .pdf files on this page right now, so you may need to use the 'download all files' link near the top of the page to get the tutorial you want in the zip file.

     

    -Gary

  • 0 in reply to Former Member

    Thank you for your answer. I made some tries and studied SDK. But still I can't program properly and something really strange happens when I program the QSPI. I'll explain:
    - I made a Planahead project with a custom VHDL code (basically it gives a square waveform every 500 ns on a pmods pin)
    - I added an embedded processor (xmp file) and created the top VHDL ('Create Top HDL' command)
    - I created another vhdl file and set as top. This file istantiates my custom vhdl and the processor (basic hierachy structure).
    - Then I exported the hardware for SDK and create a new application project (FSBL template)
    - I created a new Zynq Boot Image with the .elf file of the application project and the bit file exported from planahead.
    - Finally I programmed the QSPI (Xilinx Tools--> Program Flash) with the mcs file just created.

    Now I turn off and on the Zedboard (jumpers set properly for QSPI boot) and I see the blue led LD12 blinking for a couple of times and then nothing. I also check my pmods output (square waves every 500 ns) with an oscilloscope and I notice that there's the square waves during the blue led's blinking and then nothing. It seems like the Zedboard tries to load the QSPI but fails after some attempts.

    Is this procedure wrong?

    I found a 'solution' to this problem (which makes the all thing even stranger). In the Planahead project I changed the top istance. I had the 'great top' istance (which contains the processor and my custom vhdl), the processor vhdl (with the xmp file), and my custom VHDL file SET AS TOP! I exported the bit file of this project (which is different from a bit file of a project with only my custom vhdl, I don't understand why) and use it for the boot image (instead of the one created before). Then I program the QSPI and finally works! But I don't understand what's happening and it seems really strange to me!

    I will really thank you for your help!