Good day. I hope somecan can answer this cause it bugs me. On the reference design for PCIe root complex there are pins that go to ports that are not connected to anything. I will use the INTX_MSI_Request as example. It is an input to PCIe block and ties to an input port.
The input port is not mapped to an I/O pin in the constraints file.
When U look at elaborated schematic it is tied to GND.
I've tried enabling filters etc to look at tie offs.
Now if I do my own design and route pin to a port and unassign it, Vivado complains about it and the bitstream generation fails.
Why does Vivado treat the pin this way in the avnet ref design but if I do my own its different. Same IP, same pin, same everything.
Thxs
