Zynq PS SPI: How to constrain if SS0,SS1,SS2 are not used?

Hello,

I just tried to replicate your issue.  I generated a blank project for a MMP. 
I added a new block design.
I then added a processing system, ran the automation for that.  I then customized the PS by checking the checkbox for SPI0 and ensuring it was set to EMIO.  You are correct that the tool will not allow you to deselect the additional SS pins.

I then took your above constraints and dropped them into a file, added that to the project.  I made the M_AXI_GP0_ACLK external.  Finally, I had Vivado generate a wrapper top level.
After checking this design, I believe that you will need to define the pins.  I think because they are implemented as EMIO they must all be there.  I do not think you have to use them, so I would pin them out to pins you are not using or would effect your design.

If you move to using MIO, or chose to use a PL based AXI SPI design, I do not see that you have to bring those pins out to anything.

However, after adjusting your constraints file to be:

set_property IOSTANDARD LVCMOS33 [get_ports spi_0_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_sck_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss1_o]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss2_o]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss_io]
set_property PACKAGE_PIN AF18 [get_ports spi_0_io0_io]
set_property PACKAGE_PIN AJ18 [get_ports spi_0_io1_io]
set_property PACKAGE_PIN AH18 [get_ports spi_0_sck_io]
set_property PACKAGE_PIN AJ13 [get_ports spi_0_ss1_o]
set_property PACKAGE_PIN AJ14 [get_ports spi_0_ss2_o]
set_property PACKAGE_PIN AE18 [get_ports spi_0_ss_io]

Everything built without issue and generated a binary.

If you use these constraints, please double check the pins I chose, as I am not sure what you are hooking them up to.  I merely picked a few random pins to validate my assumption about the PS-EMIO based SPI device.
Even though, I am not using them, I had to bring them out to pins as they are defined.
I believe this is only true, if you chose to use BOARD automation, or chose to make the entire port external.

As a test, I removed the board automation generated "external" arrows.  I then clicked the + for the SPI_0 port.
I then right clicked ONLY the pins I intend to USE and said to make external.
By doing this, the TOOL now knows that only 3 pins needed to be brought out.

I of course now needed to change the constraints to match the new pin names:
set_property IOSTANDARD LVCMOS33 [get_ports SPI0_MOSI_I]
set_property IOSTANDARD LVCMOS33 [get_ports SPI0_SCLK_O]
set_property IOSTANDARD LVCMOS33 [get_ports SPI0_MISO_O]
set_property PACKAGE_PIN AF18 [get_ports SPI0_MOSI_I]
set_property PACKAGE_PIN AJ18 [get_ports SPI0_SCLK_O]
set_property PACKAGE_PIN AH18 [get_ports SPI0_MISO_O]

See if this resolves your issue and please post back, as I do not think that we have anyone on the forum that has really had to deal with this.  It would be nice to have a working solution for this for others to view.

--Dan

Hi Dan

Thanks for your efforts so far.  After I didn't get a reply at first, I implemented your second option as all the pins on our MMP are actually being used on our baseboard (its big...) so I can not go with the solution of connecting unused pins. This does work in terms of "hardware can be created".

However, when I set up the SPI using the Xilinx driver:

XSpiPs_Config *SpiConfig;
SpiConfig = XSpiPs_LookupConfig(SPI_DEVICE_ID);
Status = XSpiPs_CfgInitialize(&SpiInstance, SpiConfig, SpiConfig->BaseAddress);
XSpiPs_Reset(&SpiInstance);
Status = XSpiPs_SelfTest(&SpiInstance);

The self-test fails (for a comparison: I2C on EMIO works just fine).

I then found the following issue: http://www.xilinx.com/support/answers/47511.html
where they say that one has to connect a constant VCC to SS in case of master mode. So I added an additional constant in the block design pulling SS to 1 and WP to 0.

I also defined IO standards but not placement in my XDC file:

set_property IOSTANDARD LVCMOS33 [get_ports spi_0_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_sck_io]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss1_o]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss2_o]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss_o]
set_property IOSTANDARD LVCMOS33 [get_ports spi_0_ss_t]
set_property PACKAGE_PIN AF18 [get_ports spi_0_io0_io]
set_property PACKAGE_PIN AJ18 [get_ports spi_0_io1_io]
set_property PACKAGE_PIN AH18 [get_ports spi_0_sck_io]

and additionally added

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

to the XDC file. Re-implemented the design and... Self-Test still fails.
I'll be posting an update as soon as I have a running implementation. I guess I will switch to using an AXI SPI in the PL :/

-m Jon

I know this is a bit late but seeing as how no solution has yet been posted someone might find it useful.

If you create a top level HDL file without the unused spi ports declared above the processing system wrapper file you should be able to just leave the unused ports out of the constraints file since they are not brought out at the top level. In the below VHDL example only spi_0_io0_io and spi_0_sck_io need to be constrained since spi_0_io1_io, spi_0_ss1_o, spi_0_ss2_o, and spi_0_ss_io are not in the top level.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity example_top is
tPort
t(
ttspi_0_io0_iot: inout STD_LOGIC;
ttspi_0_sck_iot: inouttSTD_LOGIC;
tt
ttDDR_addr t: inout STD_LOGIC_VECTOR ( 14 downto 0 );
ttDDR_ba tt: inout STD_LOGIC_VECTOR ( 2 downto 0 );
ttDDR_cas_n t: inout STD_LOGIC;
ttDDR_ck_n t: inout STD_LOGIC;
ttDDR_ck_p t: inout STD_LOGIC;
ttDDR_cke t: inout STD_LOGIC;
ttDDR_cs_n t: inout STD_LOGIC;
ttDDR_dm tt: inout STD_LOGIC_VECTOR ( 3 downto 0 );
ttDDR_dq tt: inout STD_LOGIC_VECTOR ( 31 downto 0 );
ttDDR_dqs_n t: inout STD_LOGIC_VECTOR ( 3 downto 0 );
ttDDR_dqs_p t: inout STD_LOGIC_VECTOR ( 3 downto 0 );
ttDDR_odt t: inout STD_LOGIC;
ttDDR_ras_n t: inout STD_LOGIC;
ttDDR_reset_n t: inout STD_LOGIC;
ttDDR_we_n t: inout STD_LOGIC;
ttFIXED_IO_ddr_vrn: inout STD_LOGIC;
ttFIXED_IO_ddr_vrp: inout STD_LOGIC;
ttFIXED_IO_mio t: inout STD_LOGIC_VECTOR ( 53 downto 0 );
ttFIXED_IO_ps_clk : inout STD_LOGIC;
ttFIXED_IO_ps_porb: inout STD_LOGIC;
ttFIXED_IO_ps_srstb: inout STD_LOGIC
t);
end example_top;

architecture structural of example_top is

signal dummy_io1t:tstd_logic;
signal dummy_ss0t:tstd_logic;

begint
t
tdummy_ss0 <= '1';
tARM : entity work.REX_ARM_wrapper
tport map(
ttCLK_100MHzt=>tclk_100,
ttDDR_addrt=>tDDR_addr,
ttDDR_batt=>tDDR_ba,
ttDDR_cas_nt=>tDDR_cas_n,
ttDDR_ck_nt=>tDDR_ck_n,
ttDDR_ck_pt=>tDDR_ck_p,
ttDDR_ckett=>tDDR_cke,
ttDDR_cs_nt=>tDDR_cs_n,
ttDDR_dmtt=>tDDR_dm,
ttDDR_dqtt=>tDDR_dq,
ttDDR_dqs_nt=>tDDR_dqs_n,
ttDDR_dqs_pt=>tDDR_dqs_p,
ttDDR_odttt=>tDDR_odt,
ttDDR_ras_nt=>tDDR_ras_n,
ttDDR_reset_nt=>tDDR_reset_n,
ttDDR_we_nt=>tDDR_we_n,
ttFIXED_IO_ddr_vrn=>tFIXED_IO_ddr_vrn,
ttFIXED_IO_ddr_vrp=>tFIXED_IO_ddr_vrp,
ttFIXED_IO_miot=>tFIXED_IO_mio,
ttFIXED_IO_ps_clkt=>tFIXED_IO_ps_clk,
ttFIXED_IO_ps_porb=>tFIXED_IO_ps_porb,
ttFIXED_IO_ps_srstb=>tFIXED_IO_ps_srstb,
ttspi_0_io0_iot=> spi_0_io0_io,
ttspi_0_io1_iot=> dummy_io1,
ttspi_0_sck_iot=> spi_0_sck_io,
ttspi_0_ss1_ot=> open,
ttspi_0_ss2_ot=> open,
ttspi_0_ss_iot=> dummy_ss0
t);
t
end structural;