hi everyone!
I created a castum peripheral that contains 6 registers that by them i can talk with my
hardware (i work with ZedBoard). I modified user_logic file that contains my own design (that contains an hierarchy).
I did simulation to the user_logic file and the rasults were good.
But when i exporte that to SDK and run i get wrong results.
what can i do?
thanks
The Avnet Developing Zynq
-7000 All Programmable SoC Hardware (Vivado 2013.3) Speedway design workshop lab 7 details how to develop and add a custom HDL peripheral to a Zynq based design. You might want to go through the presentation and design labs to make sure you are following the complete design procedure. Lab 8 of the workshop shows how to use the Vivado Analyzer tool to help debug your hardware design as well. There are labs available for both the ZedBoard and the MicroZed board.
You can download the Speedway material here: http://www.zedboard.org/support/trainings-and-videos
-Gary
