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Create a custom peripheral with Vivado 2013.2

mangibu

Hi,

with XPS I used the u201ECreate and Import Peripheral Wizardu201D to create a custom peripheral (In my case 5 software accessible registers).

How can I do this in Vivado? With the IP-Integrator? Which IP I have to use?

Thanks a lot for helping.

Best regards

Michael

  • 0

    the way i have have integrated my XPS files with vivado is first i make a new vivado project and import my custom peripheral from XPS into that new project. you have to manually add the libraries (proc_common_v3_00_a, axi_lite_ipif_v1_01_a, which are located on my computer here: C:Xilinx14.5ISE_DSEDKhwXilinxProcessorIPLibpcores, and  whatever your user_logic library is under) to the project. once you can successfully build you IP without errors you can use the Package IP, which is located under the Tools tab.  you can use this to crate an IP module.  Once you have crated a new IP block you can create a new project and then create a new block Design under IP Integrator.  To use your new IP you need to add it to your Repository Manager.  to do this you can click on Project setting then select the IP icon on the left and under Add Repository you can go to the last project you saved and select it.  you will see your IP in the low IP in Selected Repository box.  once you say ok you can go to your IP Catalog and your IP will be under BaseIP if you didnt change the default when you where doing your package. 

    I would also read these:
    UG939  pages 39-47
    or
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug939-vivado-designing-with-ip-tutorial.pdf

    and

    http://zedboard.org/content/creating-base-zynq-design-vivado-ipi-20132

    and

    http://www.xilinx.com/support/answers/56609.htm

  • 0

    have zed and micro zed
    I can do most things that are in the app notes, etc...build a hardware model, export to sdk, write code access simple PL stuff (i.e. buttons, the io, etc)....but...
    lets say I want to build a custom fpga interface..use the io ports as outside world in's outs, but have gates/d flops, etc process this data...this is  radar app...then, get the processed data into the PS side to chunk out the Ethernet....sounds simple.
    I've tried doing custom axi modules, tried adding some vhdl code into the so called axi module template...etc...
    I'd expect you'd somehow add this vhdl code , tweek some stuff in an axi module , and then a "blue block" IP would be created that you could drop in to vivado and it would work...
    I can not for the life of me figure this out..I got something to work but it chunked in the entire zynq 7020 part...
    is there some example out there that does this?...I see all kinds of examples that are just way outside the scope of what I need to do....?
    anybody out there have something "simple" that does this?..example?....
    let meknow
    jwyoungster AT Verizon DOT net.
    thanks....
    (been at this vivado since dec)