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Using Xilinx Tools Forum Using Vivado, vhdl component get no Clock
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Related

Using Vivado, vhdl component get no Clock

Former Member
Former Member over 11 years ago

Hey,
I have a problem getting a clock signal. As you see in the picture http://pl.vc/2l3wr did I create a fabric clock in the PL section and wired it to my own IP.





Here is my Code for the IP:


entity LEDSANIM is
    Port (      CLK_IN : in std_logic;  
                RESET_IN : in std_logic;   
                LEDS_OUT : out std_logic_vector(7 downto 0) );
end LEDSANIM;

architecture Behavioral of LEDSANIM is
signal Q : std_logic_vector(7 downto 0) := "11110000";


begin

    process(CLK_IN,RESET_IN)
    begin
   
    if RESET_IN = '0' then
        Q<="00000000";
    end if;
   
    if rising_edge(CLK_IN) then

            Q<="11111111";

    end if;
   

   
    end process;
   
LEDS_OUT<=Q;

end Behavioral;




I only see the first 4 LEDS active on the Board.


I look now for more than a week for a solution but didnt find anything in the documention or forum.

Would be great if someone can help me

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  • Former Member
    0 Former Member over 11 years ago

    It looks like you have loaded your bitstream, probably via JTAG without initializing the Zynq PS (Processor System). The PS system blocks, including the FCLK_CLK0 you are sending to the PL (Programmable Logic) section of the Zynq device, must be initialized either during the First Stage Boot Loader or by ps7_init.tcl in the SDK.

     

    Export your design to the SDK and build a simple application ( hello_world will be fine) and BSP. Then launch or run the application within the SDK. This should run the ps7_init.tcl script and initialize the PS. Once the PS has been initialized your logic should be clocked and the process should operate as you expected.

     

    -Gary

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  • Former Member
    0 Former Member over 11 years ago

    Oh my god I realy forgett this.
    Thank you a lot!

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