Hello,
has anyone managed to successfully implement the Xilinx Video In to AXI4 Stream core?
Background:
As input, I use an CMOS active pixel sensor which provides image data, blanking signals and the pixel clock.
As output, I use the ZedBoard VGA.
As Designtool I use Vivado 2013.4.
Used Xilinx IP:
TPG - Test Pattern Generator
VTC - Video Timing Controller
VidOut - AXI4 Stream to Video Out Core
VidIn - Video In to AXI4 Stream core
What I have tried so far:
TPG -> VidOut -> VGA
VTC -----^
This works pretty well. See also,
(1) http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Can-t-get-quot-AXI4-Stream-to-Video-Out-quot-block-to-work/td-p/371711
What I want (and still try to set up properly):
Sensor input -> VidIn -> VidOut -> VGA
...................................'-> VTC -^
The constraints for the VidIn are set as mentioned in the Avnet FMC Imageon Tutorial "Creating a Video Design From Scratch Tutorial -14.4" ((2) http://www.xilinx.com/esp/video/refdes_listing.htm), except that I use my sensor input.
Unfortunately, it doesn't generate the expected result.
Debugging so far (if I didn't miss something):
- I scoped the VidIn Axi4s output and it seems to work properly. With my sensor input and with synthetic input
- and so does the VTC, generating the wanted signals.
- the VidOut provides no output (?)
-> the VidOut is constrained like mentioned above (in 2)
Any hints would be appreciated.
Thank you in advance.
