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Using Xilinx Tools Forum Issue with FIR Compiler V7.2 in RFSoC Design
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  • fir
  • vivado
  • Super Sample Rate
  • rfsoc
Related

Issue with FIR Compiler V7.2 in RFSoC Design

PaulBray
PaulBray 4 months ago

I have an RFSoC Design using Vivado 2020.2 where I have an data stream coming from the RFDC Block at 1536 M Sample Per Second (MSpS).  The fabric won't clock at this rate so the RFDC block gives me a 8 sample wide stream blocking at 192 MHz.  The stream feeds an FIR Block where it is low pass filtered and decimated by 6 to give me 256 MSpS. This stream is still clocked at 192 MHz and we see 2 samples per cycle with only every 2 of 3 cycles active.  The trouble is that if I measure the frequency response of the filter, it's rubbish.  Sharp dips of 10 dB or more in the passband response at regular intervals where it should be flat to within less than a dB.

If I change the filter configuration to not decimate and follow it be a separate block that decimates by 6 I see the expected flat response.  I only have the filter from integer decimation by 6 to single rate, it uses the same coefficients etc.

The work around is expensive, the DSP slice requirement goes from 120 to 680.  

Has anyone else seen anything like this?

I hate to blame the tools, and the FIR block is quite mature, but maybe operating at "Super Sample Rate" as Xilinx describe it in PG149 is a bit bleeding edge. 

Best Regards

Paul

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  • PaulBray
    PaulBray 4 months ago +1

    I think I can answer my own problem after more experimentation.

    The filter described above uses 85 coefficients, but the Vivado design pads this to 90 (divisible by 6 I guess).  While the original 85 coefficients…

  • PaulBray
    PaulBray 4 months ago

    I think I can answer my own problem after more experimentation.

    The filter described above uses 85 coefficients, but the Vivado design pads this to 90 (divisible by 6 I guess).  While the original 85 coefficients were symmetrical, the padded version can't be.  I had let the design infer the coefficient structure and it had decided that it was symmetrical.  If I force the structure to non-symmetrical the filter response looks fine.  The DSP slice requirement remains at 120 as well.

    I have other Super Sample Rate filters in my design where the symmetrical coeffients don't need to be padded out or could be padded out in a symmetrical fashion, and these were also showing issues until I force their coefficient structure to non-symmetrical.  The single example that I had of a working Super Sample Rate filter had inferred a non-symmetrical coefficient structure.

    Best Regards

    Paul

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