Does changing RX lane rate between 300 and 600 Mbps change RX CSI-2 MIPI D-PHY IP topology (HDL code of soft IP)?
Good Day Dear ,
In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which is tuned to receive CSI-2 traffic at 300 Mbps per la
In our UlraScale+ based project we utilize RX MIPI D-PHY (4.2) which is tuned to receive CSI-2 traffic at 300 Mbps per lane with 4 lanes. With incoming traffic at 300 Mbps per lane everything works without issues, as expected. Also it was reviewed an articlehttps://support.xilinx.com/s/article/69530?language=en_USwhere Xilinx recommended to use the same lane rate for RX and TX.
But as a part of development a number of experiments were performed and two of them are described below (see Table 1 below):
1) a simplex transmission was performed at 375 Mbps when RX had still been tuned to 300 Mbps. In the performed experiment the expected correct data was received.
2) In the second experiment the lane rate of incoming unidirectional traffic was 600 Mbps. Same behavior - the correct data was received by Xilinx RX D-PHY, which was configured to 300 Mbps.
As per described observations Xilinx D-PHY RX tuned for lower lane bitrate successfully receives doubled bitrate CSI-2 traffic. This behavior rises a question: does Xilinx RX MIPI D-PHY IP have different topologies at least for 300 and 600 Mbps configurations ( also interesting other bitrates < 1500Mbps)? Or just constraints is a subject for changing?
