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Versal VE2302 Hardware Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents
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Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas
iksevas 14 days ago

Brand new forum covering the release of the VE2302 Development Kit and the Versal AI Edge VE2302 SOM by Avnet / Tria-Technologies. Please ask any questions you have here when you get the chance!

Available documents are at the product page websites:

http://avnet.me/ve2302-dk

http://avnet.me/ve2302-som

Documentation that is currently publicly available is at TECHNICAL DOCUMENTS tab on those web pages. Scroll / navigate around and you should find them.

There is a BDF (board definition file) posted to the Avnet Github: Avnet/bdf: Avnet Board Definition Files

There are also a couple of repositories covering the VE2302 OOB for HW and PETALINUX in the Avnet GITHUB. This design is used for the Getting Started Guide. 

More reference designs will begin to be posted to the sites / repos as they become available.

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  • dyessgg
    dyessgg 13 days ago in reply to dyessgg +1
    I found it after clicking through 3 links. 29 Weeks and $1,850 for the development kit. Not a bad price for a Versal chip.
  • iksevas
    iksevas 13 days ago in reply to dyessgg +1
    PNs: AES-VE2302-DK-G for Development Kit 100-kits (SOM/Carrier Card) scheduled to arrive mid-March over don’t run into issues with PCB procurement.
Parents
  • kboal
    kboal 9 days ago

    Another request for schematics please. We need this information to determine I/O location constraints for our custom design that we are prototyping on this board and more broadly for when we integrate the SOM onto a custom board. 

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  • iksevas
    iksevas 9 days ago in reply to kboal

    Please review all of the available user guides (SOM, Carrier Card, as well as CC Design Guide). All pinning information and schematic snippets exist there. As mentioned previously we are working to post a master constraints file that will aid customers in building their own Vivado designs. This is due soon.

    otherwise, for schematics you need to get with your local field engineering team for Avnet who can submit an official request for the schematics pdf.

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  • iksevas
    iksevas 9 days ago in reply to kboal

    Please review all of the available user guides (SOM, Carrier Card, as well as CC Design Guide). All pinning information and schematic snippets exist there. As mentioned previously we are working to post a master constraints file that will aid customers in building their own Vivado designs. This is due soon.

    otherwise, for schematics you need to get with your local field engineering team for Avnet who can submit an official request for the schematics pdf.

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